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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TC1765T датащи(PDF) 54 Page - Infineon Technologies AG |
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TC1765T датащи(HTML) 54 Page - Infineon Technologies AG |
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54 / 88 page  TC1765 Data Sheet 50 V1.2, 2002-12 Preliminary Clock Generation Unit The Clock Generation Unit (CGU) in the TC1765, shown in Figure 16, consists of an oscillator circuit and a Phase-Locked Loop (PLL). The PLL can convert a low-frequency external clock signal to a high-speed internal clock for maximum performance. The PLL also has fail-safe logic that detects degenerate external clock behavior such as abnormal frequency deviations or a total loss of the external clock. It can execute emergency actions if it looses its lock on the external clock. In general, the CGU is controlled through the System Control Unit (SCU) module of the TC1765. Figure 16 Clock Generation Unit Block Diagram M C A 04974 O scilla tor Circu it XT AL 1 XT AL2 & f OS C Ph a se Detec t. VC O N Divid er PLL f VC O f SYS S yste m _ CLK Lock Dete ctor OS C _ OK D e ep Slee p BY PAS S 1 0 MU X Clock Generation Unit CGU System C ontrol U nit SC U K Divid e r Re giste r PLL _ CL C KD IV L O C K PL L BYP |
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