SC724/SC725

11

Output Capacitor

A 1µF ceramic capacitor is normally used at the VOUT pin

to suppress output noise and provide smooth voltage to

the load. If a larger output capacitance value is used, the

input inrush current should be considered because the

power-on transient is also dependent on the output

capacitor value. Note that SC725 has longer Turn-on Delay

Time and Rising Time than SC724. If a larger output

capacitor is used, SC725 could significantly improve input

inrush current during power-on process.

Board Layout Considerations

Fig. 1 shows a typical application circuit with PCB induc-

tance on the circuit board. An important objective of the

layout is to minimize the PCB inductance by reducing the

length and increasing the width of the traces. The input

capacitor C1 and output capacitor C2 need to be placed

close to the SC724/SC725. To analyze the stray inductance,

Fig. 1 shows three current loops during the opening or

closing of the load switch. The magnitude of the voltage

ringing at VIN or VOUT pin is related to the PCB stray

inductance and the placement of the capacitors. It is

important to keep the voltage ringing below the maximum

voltage rating of the SC724/SC725.

Application Information

Operation

The SC724/SC725 is an integrated high-side PMOS load

switch that is designed to support up to 2A continuous

output current and operate from an input voltage from

1.1V to 3.6V. The internal PMOS pass element has a very

low ON resistance of 36mΩ (typical) at V

SC724/SC725 also provides ultra-low shutdown and qui-

escent current for extended battery life during applica-

tion off and standby states.

SC725 provides longer Turn-on Delay Time and Rising

Time, which can help reduce inrush current and voltage

drop on the input supply rail during power on.

SC724 provides shorter Turn-on Delay and Rising Time for

applications where immediate response is required.

Output Voltage Pull-down

The SC725 also includes an automatic output discharge

function. It employs a 220Ω (typical) discharge path to

ground when the EN pin is disabled.

Enable

The EN pin controls the ON/OFF states of the load switch.

Pulling the EN pin HIGH turns on the load switch. Pulling

the EN pin LOW turns off the load switch. The EN pin

incorporates a 5.0MΩ (typical) pull-down resistor, so that

when the EN pin is floating the SC724/SC275 is disabled.

Input Capacitor

In order to reduce the effects of voltage drop, noise, and

bounce at the VIN pin, a filter/decoupling capacitor

between VIN to GND is recommended. A 1µF ceramic

capacitor is sufficient for most application conditions.

However, it should be noted that suppressing bounce at

input loop after EN is changed from HIGH to LOW can

require greater capacitor values depending on particular

designs. During certain shutdown conditions, as in the

case when input power supply is abruptly removed, the

input voltage may tend to drop faster than the output

voltage. In this event a reverse current, through the body

diode of internal PMOS FET, from VOUT to VIN can occur.

To limit this reverse current, the Cin value should be

selected greater than the Cout value.

C1

C2

VIN

VOUT

GND

1uF

1uF

+

-

SC724/SC725

Figure 1 - PCB Circuit with Equivalent Parasitic

Inductance

Evaluation Board Information

The Top Layer and Bottom Layer of a standard evaluation

board are shown in Fig. 2 and Fig. 3, respectively.

Both T1 and T2 test points are Kelvin connections which

can be used to minimize the measurement error of R

To enable the part, a jumper can be used between VIN

and EN on J1. To disable the part, a jumper can be con-

nected between EN and GND on J1.