GS6152 datasheet(21/80 Pages) SEMTECH

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GS6152

Final Data Sheet

Rev.2

PDS-060984

July 2015

21 of 80

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Figure 4-2: LOS Threshold at 100mV Input Swing vs. SDI Data Rates for a Nominal

DEVICE_SPECIFIC_LOS_THRESHOLD of 53

Strength detection is unaffected by the Trace EQ settings in INPUT_CONTROL_REG_0.

When edge detection is used as the method of LOS detection the corresponding GPIO

pin will be HIGH (signal lost) when no transitions are detected on the selected input. The

corresponding GPIO pin will be LOW (signal present) when transitions are detected on

the input. The LOS status is also available through the LOS bit in the PLL_STATUS

4.3.2 Lock Detection

The GS6152 lock detection circuitry outputs a LOCKED status signal which indicates that

the CDR has achieved phase lock to the incoming data stream. The LOCKED signal is an

active HIGH output available to the application on any of the GPIO[3:0] multi-function

status and control pins. It is selected for output using the GPIO[3:0]_IO_SELECT and

GPIO[3:0]_SELECT bits accessible in the GPIO_CONTROL_REG_0 and

GPIO_CONTROL_REG_1 registers. By default, LOCKED is output on GPIO1.

The LOCKED status is available from the LOCKED bit in the PLL_STATUS register, and the

LOCK_LOST_STICKY bit in the STICKY_STATUS register indicates whether lock has been

lost since the bit was last cleared.

6G-SDI

3G-SDI

HD-SDI

SD-SDI

1.485

2.97

4.455

5.94

Frequency (Gb/s)

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