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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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GS1671 датащи(PDF) 28 Page - Semtech Corporation |
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GS1671 датащи(HTML) 28 Page - Semtech Corporation |
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28 / 130 page  GS1671 HD/SD SDI Integrated Receiver Data Sheet 53737 - 2 September 2012 28 of 130 Figure 4-1: GS1671 Integrated EQ Block Diagram 4.3 Serial Digital Loop-Through Output The GS1671 contains a 100 Ω differential serial output buffer which can be configured to output either a retimed or a buffered version of the serial digital input. The SDO and SDO outputs of this buffer can interface directly to a 1.485Gb/s-capable, SMPTE compliant Gennum cable driver. See 5.3 Typical Application Circuit on page 125. When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the serial input. When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version of the serial input, bypassing the internal reclocker. The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both SDO and SDO pins are set to VDD and remain static. The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked (LOCKED pin is LOW). When muted, the output is held static at logic ‘0’ or logic ‘1’. NOTE: the serial digital output is muted when the GS1671 is unlocked. Equalizer Output AGC SDI SDO SDI SDO AGC AGC GAIN_SEL DC Restore Table 4-1: Serial Digital Output SDO_EN/DIS RC_BYP SDO/SDO 0X Disabled 11 Re-timed 10 Buffered (not re-timed) |
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