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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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GS1670 датащи(PDF) 28 Page - Semtech Corporation |
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GS1670 датащи(HTML) 28 Page - Semtech Corporation |
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28 / 126 page  GS1670 HD/SD SDI Receiver Data Sheet 53831 - 2 September 2012 28 of 126 Figure 4-1: 27MHz Clock Sources 4.6 Lock Detect The LOCKED output signal is available by default on the STAT3 output pin, but may be programmed to be output through any one of the six programmable multi-functional pins of the device; STAT[5:0]. The LOCKED output signal is set HIGH by the Lock Detect block under the following conditions: External Crystal Connection XTAL1 XTAL2 XTAL1 XTAL2 External Clock Source Connection 16pF 16pF External Clock NC K6 K6 J6 J6 Notes: 1. Capacitor values listed represent the total capacitance, including discrete capacitance and parasitic board capacitance. 2.XTAL1 serves as an input, which may alternatively accept a 27MHz clock source. Table 4-3:Input Clock Requirements Parameter Min Typ Max UOM Notes XTAL1 Low Level Input Voltage (Vil) −− 20% of VDD_IO V 3 XTAL1 High Level Input Voltage (Vih) 80% of VDDIO −− V3 XTAL1 Input Slew Rate 2 −− V/ns 3 XTAL1 to XOUT Prop. Delay (High to Low) 1.3 1.5 2.3 ns 3 XTAL1 to XOUT Prop. Delay (Low to High) 1.3 1.6 2.3 ns 3 NOTES: Valid when the cell is used to buffer an external clock source which is connected to the XTAL1 pin, then nothing should be connected to the XTAL2 pin. |
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