List of figures

VN7007ALH

List of figures

Figure 1: Block diagram ..............................................................................................................................5

Figure 2: Configuration diagram (top view).................................................................................................6

Figure 3: Current and voltage conventions.................................................................................................7

Figure 4: Switching times and Pulse skew ...............................................................................................13

Figure 5: TDSTKON..................................................................................................................................13

Figure 6: OFF-state output current ...........................................................................................................15

Figure 7: Standby current .........................................................................................................................15

Figure 8: IGND(ON) vs. Tcase .................................................................................................................15

Figure 9: Logic Input high level voltage ....................................................................................................15

Figure 10: Logic Input low level voltage....................................................................................................15

Figure 11: High level logic input current ...................................................................................................15

Figure 12: Low level logic input current ....................................................................................................16

Figure 13: Logic Input hysteresis voltage .................................................................................................16

Figure 14: Undervoltage shutdown...........................................................................................................16

Figure 15: On-state resistance vs. Tcase .................................................................................................16

Figure 16: On-state resistance vs. VCC ...................................................................................................16

Figure 17: Turn-on voltage slope ..............................................................................................................16

Figure 18: Turn-off voltage slope ..............................................................................................................17

Figure 19: Won vs Tcase ..........................................................................................................................17

Figure 20: Woff vs Tcase ..........................................................................................................................17

Figure 21: ILIMH vs. Tcase.......................................................................................................................17

Figure 22: Turn-off output voltage clamp..................................................................................................17

Figure 23: OFF-state open-load voltage detection threshold ...................................................................17

Figure 24: Vsense clamp vs Tcase...........................................................................................................18

Figure 25: Vsenseh vs Tcase ...................................................................................................................18

Figure 26: Application diagram .................................................................................................................20

Figure 27: Simplified internal structure .....................................................................................................20

Figure 28: CurrentSense and diagnostic – block diagram........................................................................22

Figure 29: CurrentSense block diagram ...................................................................................................23

Figure 30: Analogue HSD – open-load detection in off-state ...................................................................24

Figure 31: Open-load / short to VCC condition.........................................................................................25

Figure 32: Maximum turn off current versus inductance ..........................................................................27

Figure 33: Octapak on two-layers PCB (2s0p to JEDEC JESD 51-5)......................................................28

Figure 34: Octapak on four-layers PCB (2s2p to JEDEC JESD 51-7) .....................................................28

Figure 35: Rthj-amb vs PCB copper area in open box free air conditions ...............................................29

Figure 36: Octapak thermal impedance junction ambient single pulse ....................................................29

Figure 37: Thermal fitting model for Octapak ...........................................................................................30

Figure 38: Octapak package dimensions .................................................................................................31

Figure 39: Octapack reel 13" ....................................................................................................................33

Figure 40: Octapak carrier tape ................................................................................................................34

Figure 41: Octapak schematic drawing of leader and trailer tape ............................................................34

Figure 42: Octapak marking information...................................................................................................35

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