PEF2015 datasheet(21/84 Pages) INFINEON

21 / 84 page

PEF 2015

Operational Description

Semiconductor Group

12.97

capability of the MICO should prove to be insufficient for a specific application, an

external driver controlled by the TSC can be connected.

The PCM-standby function makes it possible to switch all PCM-output lines to high

impedance with a single command. Internally, the device still works normally. Only the

output drivers are switched off.

The number of time slots per 8-kHz frame is programmable in a wide range (from 4 to

128). In other words, the PCM-data rate can range between 256 kbit/s up to

8.192 Mbit/s. For time slot encoding refer to figure 7.

The number of bits per frame is defined by the PCM-mode. There are three PCM-

modes.

The timing characteristics at the PCM-interface (data rate, bit shift, etc.) can be varied in

a wide range.

The PCM-interface has to be clocked with a PCM-Data Clock (PDC) signal having a

frequency equal to or twice the selected PCM-data rate. In single clock rate operation,

a frame consisting of 32 time slots, for example, requires a PDC of 2048 kHz. In double

clock rate operation, however, the same frame structure would require a PDC of

4096 kHz.

For the synchronization of the time slot structure to an external PCM-system, a PCM-

Framing Signal (PFS) must be applied. The MICO evaluates the rising PFS edge to

reset the internal time slot counters. In order to adapt the PFS-timing to different timing

requirements, the MICO can latch the PFS-signal with either the rising or the falling PDC-

edge. The PFS-signal defines the position of the first bit of the internal PCM-frame. The

actual position of the external upstream and downstream PCM-frames with respect to

the framing signal PFS can still be adjusted using the PCM-offset function of the MICO.

The offset can then be programmed such that PFS marks any bit number of the external

frame.

Furthermore it is possible to select either the rising or falling PDC-clock edge for

transmitting and sampling the PCM-data.

Usually, the repetition rate of the applied framing pulse PFS is identical to the frame

period (125

µs). If this is the case, the loss of synchronism indication function can

be used to supervise the clock and framing signals for missing or additional clock cycles.

The MICO checks the PFS-period internally against the duration expected from the

programmed data rate. If, for example, double clock operation with 32 time slots per

frame is programmed, the MICO expects 512 clock periods within one PFS-period. The

synchronous state is reached after the MICO has detected two consecutive correct

frames. The synchronous state is lost if one bad clock cycle is found. The

synchronization status (gained or lost) can be read from an internal register and each

status change generates an interrupt.

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