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STBP110FUDJ6F датащи(PDF) 31 Page - STMicroelectronics |
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STBP110FUDJ6F датащи(HTML) 31 Page - STMicroelectronics |
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31 / 40 page ![]() STBP110 Application information Doc ID 018687 Rev 3 31/40 8.3 PCB layout recommendations ● Input capacitor C1 should be located as close as possible to the STBP110 device. It should be a low-ESR ceramic capacitor. Also the protective resistors RFLT and REN (if used) should be located close to the STBP110 (see Figure 4). ● For good thermal performance, it is preferred to couple the STBP110 exposed thermal pads with the PCB ground plane. In most designs, this requires thermal vias between the copper pads on the PCB and the ground plane. |
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