TUSB8041IPAPRQ1 datasheet(5/48 Pages) TI1

5 / 48 page

TUSB8041-Q1

www.ti.com

SLLSEE6B – JULY 2014 – REVISED JANUARY 2016

Pin Functions

I/O

DESCRIPTION

NAME

NO.

Clock and Reset Signals

Global power reset. This reset brings all of the TUSB8041-Q1 internal registers to their

GRSTz

default states. When GRSTz is asserted, the device is completely nonfunctional.

Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately

be driven by the output of an external oscillator. When using a crystal a 1-M

Ω feedback

resistor is required between XI and XO.

Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an

external oscillator this pin may be left unconnected. When using a crystal a 1-M

Ω feedback

resistor is required between XI and XO.

USB Upstream Signals

USB_SSTXP_UP

USB SuperSpeed transmitter differential pair (positive)

USB_SSTXM_UP

USB SuperSpeed transmitter differential pair (negative)

USB_SSRXP_UP

USB SuperSpeed receiver differential pair (positive)

USB_SSRXM_UP

USB SuperSpeed receiver differential pair (negative)

USB_DP_UP

I/O

USB High-speed differential transceiver (positive)

USB_DM_UP

I/O

USB High-speed differential transceiver (negative)

Precision resistor reference. A 9.53-k

Ω ±1% resistor should be connected between USB_R1

USB_R1

and GND.

USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal

USB_VBUS

USB_VBUS must be connected to VBUS through a 90.9-K

Ω ±1% resistor, and to ground

through a 10-k

Ω ±1% resistor from the signal to ground.

USB Downstream Signals

USB_SSTXP_DN1

USB SuperSpeed transmitter differential pair (positive)

USB_SSTXM_DN1

USB SuperSpeed transmitter differential pair (negative)

USB_SSRXP_DN1

USB SuperSpeed receiver differential pair (positive)

USB_SSRXM_DN1

USB SuperSpeed receiver differential pair (negative)

USB_DP_DN1

I/O

USB High-speed differential transceiver (positive)

USB_DM_DN1

I/O

USB High-speed differential transceiver (negative)

USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is

used for control of the downstream power switch for Port 1.

In addition, the value of the pin is sampled at the de-assertion of reset to determine the value

of the battery charging support for Port 1 as indicated in the Battery Charging Support

PWRCTL1/BATEN1

I/O, PD

0 = Battery charging not supported

1 = Battery charging supported

USB Port 1 Over-Current Detection. This pin is used to connect the over current output of the

downstream port power switch for Port 1.

0 = An over current event has occurred

OVERCUR1z

I, PU

1 = An over current event has not occurred

This pin can be left unconnected if power management is not implemented. If power

management is enabled, the external circuitry needed should be determined by the power

switch.

USB_SSTXP_DN2

USB SuperSpeed transmitter differential pair (positive)

USB_SSTXM_DN2

USB SuperSpeed transmitter differential pair (negative)

USB_SSRXP_DN2

USB SuperSpeed receiver differential pair (positive)

USB_SSRXM_DN2

USB SuperSpeed receiver differential pair (negative)

USB_DP_DN2

I/O

USB High-speed differential transceiver (positive)

USB_DM_DN2

I/O

USB High-speed differential transceiver (negative)

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