TUSB8041IPAPQ1 datasheet(18/48 Pages) TI1

18 / 48 page

TUSB8041-Q1

SLLSEE6B – JULY 2014 – REVISED JANUARY 2016

www.ti.com

8.5.6 Product ID MSB Register

Table 12. Register Offset 4h

Bit No.

Reset State

Table 13. Bit Descriptions – Product ID MSB Register

Bit

Field Name

Access

Description

Product ID MSB. Most significant byte of the product ID assigned by

Texas Instruments; the default value of this register is 81h representing

the MSB of the product ID assigned by Texas Instruments. The value

7:0

productIdMsb

RO/RW

may be over-written to indicate a customer product ID.

This field is read/write unless the OTP ROM VID and OTP ROM PID

values are non-zero. If both values are non-zero, the value when reading

this register will reflect the OTP ROM value.

8.5.7 Device Configuration Register

Table 14. Register Offset 5h

Bit No.

Reset State

Table 15. Bit Descriptions – Device Configuration Register

Bit

Field Name

Access

Description

Custom strings enable. This bit controls the ability to write to the

Manufacturer String Length, Manufacturer String, Product String Length,

Product String, and Language ID registers

0 = The Manufacturer String Length, Manufacturer String, Product

String Length, Product String, and Language ID registers are read

customStrings

only

1 = The Manufacturer String Length, Manufacturer String, Product

String Length, Product String, and Language ID registers may be

loaded by EEPROM or written by SMBus

The default value of this bit is 0.

Custom serial number enable. This bit controls the ability to write to the

serial number registers.

0 = The Serial Number String Length and Serial Number String

registers are read only

customSernum

1 = Serial Number String Length and Serial Number String registers

may be loaded by EEPROM or written by SMBus

The default value of this bit is 0.

U1 U2 Disable. This bit controls the U1/U2 support.

0 = U1/U2 support is enabled

1 = U1/U2 support is disabled, the TUSB8041-Q1 will not initiate or

accept any U1 or U2 requests on any port, upstream or downstream,

unless it receives or sends a Force_LinkPM_Accept LMP. After

receiving or sending an FLPMA LMP, it will continue to enable U1

u1u2Disable

and U2 according to USB 3.0 protocol until it gets a power-on reset

or is disconnected on its upstream port.

When the TUSB8041-Q1 is in I2C mode, the TUSB8041-Q1 loads this bit

from the contents of the EEPROM.

When the TUSB8041-Q1 is in SMBUS mode, the value may be over-

written by an SMBus host.

RSVD

Reserved. This bit is reserved and returns 1 when read.

Submit Documentation Feedback

TUSB8041IPAPQ1 датащи(PDF) 18 Page - Texas Instruments

TUSB8041IPAPQ1 датащи(HTML) 18 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL