Signal 1

GND Plane

Power Plane

Signal 2

TS3USB221

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SCDS220I – NOVEMBER 2006 – REVISED JANUARY 2016

10 Power Supply Recommendations

frequency noise to provide better load regulation across the frequency spectrum.

11 Layout

11.1 Layout Guidelines

traces.

The high-speed D+/D– traces should always be matched lengths and must be no more than 4 inches, otherwise

the eye diagram performance may be degraded. A high-speed USB connection is made through a shielded,

twisted pair cable with a differential characteristic impedance. In the layout, the impedance of D+ and D– traces

should match the cable characteristic differential impedance for optimal performance.

Route the high-speed USB signals using a minimum of vias and corners which will reduce signal reflections and

impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of

picking up interference from the other layers of the board. Be careful when designing test points on twisted pair

lines; through-hole pins are not recommended.

When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This

reduces reflections on the signal traces by minimizing impedance discontinuities.

Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,

mounting holes, magnetic devices or IC’s that use or duplicate clock signals.

Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is unavoidable, then

the stub should be less than 200 mm.

Avoid crossing over anti-etch, commonly found with plane splits.

A printed circuit board with at least four layers is recommended because of high frequencies associated with the

USB; two signal layers separated by a ground and power layer as shown in Figure 19.

Figure 19. Four-Layer Board Stack-Up

The majority of signal traces should run on a single layer, preferably Signal 1. Immediately next to this layer

should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in the ground or

power plane. When running across split planes is unavoidable, sufficient decoupling must be used. Minimizing

the number of signal vias reduces EMI by reducing inductance at high frequencies. For more information on

layout guidelines, see High Speed Layout Guidelines (SCAA082) and USB 2.0 Board Design and Layout

Guidelines (SPRAAR7).

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