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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STAP16DPPS05XTTR датащи(PDF) 24 Page - STMicroelectronics |
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STAP16DPPS05XTTR датащи(HTML) 24 Page - STMicroelectronics |
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24 / 33 page  Error detection mode functionality STAP16DPPS05 24/33 DocID024306 Rev 6 Figure 22. Error detection sequence AM13670v1 Ignore On the rising edge of f irst CLK pulse af ter the detection, the SDO provides the Output status f eedback with the sequence Out 15; Out 14…Out 0. In this case all the outputs are in f ault condition (Open or Short) This OE/DM2 pulse put the device in Normal Mode Condition af ter EDM test Turn ON the output with the OE/DM2 pin and wait 1 µs to have the correct output status acquisition. During this time a minimum of three CLK pulses are required (2 at the beginning and 1 at the end) to rewrite the shif t register. OE/DM2 and LE/DM1 sequence signals to start the error detection sequence Feeding 16 bit of CLK signal af ter entering the EDM, the SDI signal, set to 1, is loaded in the shif t register This LE/DM1 pulse latch the data to the outputs |
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