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M95160-DRMF4TP датащи(PDF) 20 Page - STMicroelectronics

номер детали M95160-DRMF4TP
подробное описание детали  Automotive 16-Kbit serial SPI bus EEPROMs
PDF  42 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95160-DRMF4TP датащи(HTML) 20 Page - STMicroelectronics

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Instructions
M95160-A125 M95160-A145
20/42
DocID023726 Rev 6
4.6
Write to Memory Array (WRITE)
The WRITE instruction is used to write new data in the memory.
As shown in Figure 10, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address bytes, and at least one data byte are then
shifted in (MSB first), on Serial Data Input (D). The instruction is terminated by driving Chip
Select (S) high at a data byte boundary. Figure 10 shows a single byte write.
Figure 10. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
A Page write is used to write several bytes inside a page, with a single internal Write cycle.
For a Page write, Chip Select (S) has to remain low, as shown in Figure 11, so that the next
data bytes are shifted in. Each time a new data byte is shifted in, the least significant bits of
the internal address counter are incremented. If the address counter exceeds the page
boundary (the page size is 32 byte), the internal address pointer rolls over to the beginning
of the same page where next data bytes will be written. If more than 32 byte are received,
only the last 32 byte are written.
For both Byte write and Page write, the self-timed Write cycle starts from the rising edge of
Chip Select (S), and continues for a period tW (as specified in Table 15).
The instruction is discarded, and is not executed, under the following conditions:
•
if a Write cycle is already in progress
•
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits
•
if one of the conditions defined in Section 3.4.1 is not satisfied
Note:
The self-timed Write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit
is read as “0” and a programmed bit is read as “1”.



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