DocID023507 Rev 5

29/40

M24512-A125

DC and AC parameters

39

Table 11. 400 kHz AC characteristics

Symbol

Alt.

1. Test conditions (in addition to those in Table 7 and Table 8).

Min.

Max.

Unit

Clock frequency

-

400

kHz

Clock pulse width high

600

-

ns

Clock pulse width low

1300

-

ns

2. Characterized value, not tested in production.

20

120

ns

Input signal rise time

(4)

4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the

I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when

(4)

ns

Input signal fall time

(4)

(4)

ns

100

-

ns

0

-

ns

5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

Data out hold time

100

-

ns

Clock low to next data valid (access time)

-

900

ns

600

-

ns

600

-

ns

600

-

ns

Time between Stop condition and next Start

condition

1300

-

ns

7. WC=0 set up time condition to enable the execution of a WRITE command.

0

-

µs

8. WC=0 hold time condition to enable the execution of a WRITE command.

1

-

µs

Write time

-

4

ms

-

Pulse width ignored (input filter on SCL and

SDA) - single glitch

-80

ns