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M93Cx6-DRE

Instructions

31

5.1

Read Data from Memory

The Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q).

When the instruction is received, the op-code and address are decoded, and the data from

the memory is transferred to an output shift register. A dummy 0 bit is output first, followed

by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are

triggered by the rising edge of Serial Clock (C). The M93Cx6-DRE automatically increments

the internal address register and clocks out the next byte (or word) as long as the Chip

Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or

words) and a continuous stream of data can be read (the address counter automatically rolls

over to 00h when the highest address is reached).

5.2

Erase and Write data

5.2.1

Write Enable and Write Disable

The Write Enable (WEN) instruction enables the future execution of erase or write

instructions, and the Write Disable (WDS) instruction disables it. When power is first

applied, the M93Cx6-DRE initializes itself so that erase and write instructions are disabled.

After a Write Enable (WEN) instruction has been executed, erasing and writing remains

power-on reset threshold voltage. To protect the memory contents from accidental

corruption, it is advisable to issue the Write Disable (WDS) instruction after every write

cycle. The Read Data from Memory (READ) instruction is not affected by the Write Enable

(WEN) or Write Disable (WDS) instructions.

5.2.2

Write

For the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and

address bits. These form the byte or word that is to be written. As with the other bits, Serial

Data Input (D) is sampled on the rising edge of Serial Clock (C).

After the last data bit has been sampled, the Chip Select Input (S) must be taken low before

the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought low before or after

this specific time frame, the self-timed programming cycle will not be started, and the

addressed location will not be programmed. The completion of the cycle can be detected by

monitoring the READY/BUSY line, as described later in this document.

Once the Write cycle has been started, it is internally self-timed (the external clock signal on

Serial Clock (C) may be stopped or left running after the start of a Write cycle). The Write

cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an

explicit erase instruction before a Write Data to Memory (WRITE) instruction.