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M24C16-DRMF3TP датащи(PDF) 21 Page - STMicroelectronics |
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M24C16-DRMF3TP датащи(HTML) 21 Page - STMicroelectronics |
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21 / 37 page ![]() DocID025622 Rev 5 21/37 M24C16-A125 Application design recommendations 36 5 Application design recommendations 5.1 Supply voltage 5.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 6). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal Write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. 5.1.2 Power-up conditions When the power supply is turned on, the VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 6. In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal threshold voltage (this threshold is defined in the DC characteristic Table 10 as VRES). When VCC passes over the POR threshold, the device is reset and in the following state: • in the Standby power mode • deselected As soon as the VCC voltage has reached a stable value within the [VCC(min), VCC(max)] range (defined in Table 6), the device is ready for operation. 5.1.3 Power-down During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 6), the device must be in Standby power mode (that is after a STOP condition or after the completion of the Write cycle tW if an internal Write cycle is in progress). 5.2 Error correction code (ECC x 1) The error correction code (ECC x 1) is an internal logic function which is transparent for the I2C communication protocol. The ECC x 1 logic is implemented on each byte of the memory array. If a single bit out of the byte happens to be erroneous during a Read operation, the ECC x 1 detects this bit and replaces it with the correct value. The read reliability is therefore much improved. |
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