L9779WD datasheet(150/170 Pages) STMICROELECTRONICS

150 / 170 page

Functional description

L9779WD

150/170

DocID027452 Rev 5

CONFIG_REG6

Configuration register 6

Address:

0100b

Type:

R/W (write access: WRITE_CONFIG6)

Reset:

0010 0010

654

CAN_ERR_EN

NL_RST

PWL_EN_N/

SEO_EN_N

PSOFF

VDD5_UV mask

VDD5 under

voltage on SDO

WDA time base

setting

(RESPTIME)

PWL/SEO

timeout

R/W

[7] CAN_ERR_EN: CAN error handling

1: CAN error handling enabled

0: CAN error handling disabled

[6] NL_RST: Reset generation during Power latch mode when KEY_ON 0 --> 1

1: reset generated

0: reset not generated

[5] PWL_EN_N: Power latch mode enable

PWL_EN_N/SEO_EN_N: Power latch/secure engine off mode enable

1: power latch mode function is disabled (default)

0: power latch mode function is enabled

[4] PSOFF: Power supply off (VDD5, VTRK1, VTRK2, Charge-pump, internal supply) when

KEY_ON = 0 and PWL_EN_N = 1

0: switch off power supply and switch off MRD

1: do not switch off power supply and switch off MRD

[3] VDD5_UV mask

1: mask VDD5_UV

0: mask removed (default)

Note: if VDD5_UV is masked, OUTx are not automatically switched off.

[2] VDD5 under voltage on SDO

1: VDD5 under voltage event forces SDO to constantly send Low logic values whenever SDO

output is enabled, till VDD5 under voltage monitor remains active

0: this function disabled (default)

Note: as SDO gets stuck to Low upon VDD5_UV event, before any further readings, it is

recommended that this function is disabled.

[1] WDA time base setting

This bit selects the RESPTIME time base

1: (default) sets time base to 1/64 kHz

0: sets time base to 1/39 kHz

[0] PWL/SEO timeout

0: PWL timeout counter has priority over SEO (default)

1: SEO timeout counter has priority over PW

Note: if this bit is set, bit4 and bit5 of same register have no effects

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