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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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L9779WD датащи(PDF) 148 Page - STMicroelectronics |
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L9779WD датащи(HTML) 148 Page - STMicroelectronics |
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148 / 170 page  Functional description L9779WD 148/170 DocID027452 Rev 5 CONFIG_REG4 Configuration register 4 Address: 1100b Type: R/W (write access: WRITE_CONFIG4) Reset: 0000_0010 765 432 10 PWL_TIMEOUT_CONF[2:0] OFF_LCDR FDO_SEL[1:0] ISO_SRC LOCK R/W [7:5] PWL_TIMEOUT_CONF[2:0]: Power latch mode time-out configuration. 000: Disabled (default) 001: 4.7 minutes ±5% 010: 9 minutes ±5% 011: 19 minutes ±5% 100: 28 minutes ±5% 101: 37 minutes ±5% 110: 75 minutes ±5% 111: 470 ms ±5% [4] OFF_LCDR: Off state diagnosis for Low-current drive 1 = Off state diagnosis and the bias current of OUT19, OUT20 is active 0 = Off state diagnosis and the bias current of OUT19, OUT20 is disabled [3:2] F_DO_SEL[1:0]: Upstream clock ratio selection. 00: fDO= fCL/ 64(default) 01: fDO= fCL/ 16 10: fDO= fCL/ 32 11: fDO= fCL/ 128 [1] ISO_SRC: Slew-rate control for the ISO9141 serial interface (K-Line) 0 = No slew rate limitation 1 = Slew-rate limitation active [0] LOCK: Lock bit status. Set by LOCK command and cleared with UNLOCK command 1 = ALL configuration registers are locked and cannot be changed 0 = all configuration registers can be changed |
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