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M24M02-DR датащи(PDF) 28 Page - STMicroelectronics |
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M24M02-DR датащи(HTML) 28 Page - STMicroelectronics |
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28 / 38 page ![]() DC and AC parameters M24M02-DR 28/38 DocID18204 Rev 8 Table 14. 1 MHz AC characteristics Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock frequency 0 1 MHz tCHCL tHIGH Clock pulse width high 260 - ns tCLCH tLOW Clock pulse width low 400 - ns tXH1XH2 tR Input signal rise time (1) 1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz. (1) ns tXL1XL2 tF Input signal fall time (1) (1) ns tQL1QL2(2) 2. Characterized only, not tested in production. tF SDA (out) fall time 20(3) 3. With CL = 10 pF. 120 ns tDXCH tSU:DAT Data in setup time 50 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX(4) 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. tDH Data out hold time 100 - ns tCLQV(5) 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13. tAA Clock low to next data valid (access time) - 450 ns tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns tWLDL(6) 6. WC=0 set up time condition to enable the execution of a WRITE command. tSU:WC WC set up time (before the Start condition) 0 - µs tDHWH(7)(2) 7. WC=0 hold time condition to enable the execution of a WRITE command. tHD:WC WC hold time (after the Stop condition) 1 - µs tW tWR Write time - 10 ms tNS(2) - Pulse width ignored (input filter on SCL and SDA) -80 ns |
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