LNBH25SPQR datasheet(19/37 Pages) STMICROELECTRONICS

19 / 37 page

LNBH25S

I²C bus interface

DocID026736 Rev 2

19/37

I²C bus interface

Data transmission from the main microprocessor to the LNBH25S and vice versa takes

place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up

resistors to positive supply voltage must be externally connected).

6.1

Data validity

As shown in Figure 8: "Data validity on the I²C bus", the data on the SDA line must be

stable during the high semi-period of the clock. The high and low state of the data line can

only change when the clock signal on the SCL line is low.

6.2

Start and stop condition

As shown in Figure 9: "Timing diagram of I²C bus", a start condition is a transition from high

to low of the SDA line while SCL is high. The stop condition is a transition from low to high

of the SDA line while SCL is high. A stop condition must be sent before each start

condition.

6.3

Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by

an acknowledge bit. The MSB is the first to be transferred.

6.4

Acknowledge

The master (microprocessor) puts a resistive high level on the SDA line during the

acknowledge clock pulse, see Figure 10: "Acknowledge on the I²C bus". The peripheral

(LNBH25S), which acknowledges, must pull down (low) the SDA line during the

acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. The

peripheral, which has been addressed, has to generate acknowledge after the reception of

each byte, otherwise the SDA line remains at high level during the nin

th clock pulse time. In

this case, the master transmitter can generate the stop information in order to abort the

transfer. The LNBH25S doesn’t generate acknowledge if the V

CC supply is below the

undervoltage lockout threshold (4.7 V typ.).

6.5

Transmission without acknowledge

If the detection of the LNBH25S acknowledges is not necessary, the microprocessor can

use a simpler transmission: it simply waits for one clock without checking the slave

acknowledging, and sends the new data. This approach is less protected from misworking

and decreases noise immunity.

LNBH25SPQR датащи(PDF) 19 Page - STMicroelectronics

LNBH25SPQR датащи(HTML) 19 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

датащи скачать

ссылки URL