A6986F datasheet(50/72 Pages) STMICROELECTRONICS

50 / 72 page

Application notes

A6986F

50/72

DocID027739 Rev 1

frequency higher than the maximum oscillator spread (refer to Table 6 on page 11) for at

least 10 internal clock cycles.

For example: selecting RFSW = 0 to GND

the device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it

is able to synchronize to a clock signal in the range 275 kHz - 2 MHz (see Figure 41).

Anyway it is suggested to limit the frequency range within ± 20% FSW resistor nominal

frequency (see details in text below). If not spread spectrum is required, all the regulators

synchronize to a frequency higher to the maximum oscillator spread (550 kHz in the

example).

The device keeps operating in slave mode as far as the master is able to drive the SYNCH

pin faster than 275 kHz (maximum oscillator spread for 250 kHz oscillator), otherwise it goes

back into MASTER mode at the nominal oscillator frequency after successfully driving one

pulse at 250 kHz (see Figure 43) in the SYNCH line.

Figure 43. Slave to master mode transition

The external master can force a latched SLAVE mode driving the SYNCH pin low at power-

up, before the soft-start starts the switching activity. So the oscillator frequency is 250 kHz

typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise

counts to design the slope compensation. The same considerations above are also valid.

Table 12. Example of oscillator frequency selection from Table 6

Symbol

RVCC (E24 series)

RGND (E24 series)

fSW min.

fSW typ.

fSW max.

fSW



450

500

550

250kHz typ.

SLAVE mode

stand alone operation at nominal fsw

SYNCH signal

switching node

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