USB3300 datasheet(31/53 Pages) MICROCHIP

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DS00001783B-page 31

USB3300

6.1.9.2

Exiting Low Power Mode

To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3300 will begin its start-up pro-

cedure. After the PHY start-up is complete, the PHY will start the clock on CLKOUT and de-assert DIR. Once DIR has

been de-asserted, the Link can de-assert STP when ready and start operating in Synchronous Mode. The PHY will auto-

matically set the SuspendM bit to a 1 in the Function Control register.

The time from T0 to T1 is given in Table 5-2, “Electrical Characteristics: CLKOUT Start-Up,” on page 12.

Should the Link de-assert STP before DIR is de-asserted, the USB3300 will detect this as a false resume request and

return to Low Power Mode. This is detailed in section 3.9.4 of the ULPI 1.1 specification.

6.1.9.3

Interface Protection

ULPI protocol assumes that both the Link and PHY will keep the ULPI data bus driven by either the Link when DIR is

low or the PHY when DIR is high. The only exception is when DIR has changed state and a turn around cycle occurs

for 1 clock period.

In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus to a known state

while DIR is low. Two examples where this can happen is because of a slow Link start-up or a hardware reset.

Start up Protection

Upon start-up, when the PHY de-asserts DIR, the Link must be ready to receive commands and drive Idle on the data

bus. If the Link is not ready to receive commands or drive Idle, it must assert STP before DIR is de-asserted. The Link

can then de-assert STP when it has completed its start-up. If the Link doesn’t assert STP before it can receive com-

mands, the PHY may interpret the databus state as a TX CMD and transmit invalid data onto the USB bus, or make

invalid register writes.

A Link should be designed to have the default POR state of the STP output high and the data bus tri-stated. The

USB3300 has weak pull-downs on the DATA bus to prevent these inputs from floating when not driven.

In some cases, a Link may be software configured and not have control of its STP pin until after the PHY has started.

In this case, the USB3300 has an internal pull-up on the STP input pad which will pull STP high while the Link’s STP

output is tri-stated. The STP pull-up resistor is enabled on POR and can be disabled by setting the InterfaceProtectDis-

able

bit 7 of the Interface Control register.

The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STP high. Once the

Link completes its start-up, STP can be synchronously driven low.

FIGURE 6-9:

EXITING LOW POWER MODE

DIR

CLK

DATA[7:0]

STP

NXT

TURN

AROUND

LOW

POWER MODE

DATA BUS IGNORED (SLOW LINK)

IDLE (FAST LINK)

IDLE

Slow Link Drives Bus

Idle and STP low

Fast Link Drives Bus

Idle and STP low

...

Note: Not to Scale

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