DLPC6401 datasheet(39/50 Pages) TI1

39 / 50 page

DLPC6401

www.ti.com

DLPS031C – DECEMBER 2013 – REVISED AUGUST 2015

Table 13. DMD I/F, PCB(1) Interconnect Min and Max Length Limitations (Note Operating Frequency

Dependencies)(2) (continued)

SIGNAL ROUTING LENGTH

BUS

SIGNAL GROUP

MAX(3)(4)

UNIT

MIN(3)

120 MHz

106.7 MHz

96 MHz

87.7 MHz

DMD_SAC_CLK,

DMD_SAC_BUS,

512

5906

mil

DMD (SDR)

DMD_DAD_OEZ,

(13)

(150)

(mm)

DMD_DAD_STRB,

DMD_DAD_BUS

spacer

•

Number of layer changes:

–

Minimize layer changes

•

Stubs:

–

Stubs should be avoided

Termination requirements:

DMD DDR data:

Specifically: DMD_D(23-0)

External [5-

Ω] series termination (at the transmitter)

DMD DDR clock

Specifically: DMD_DCLK

External [5-

Ω] series termination

DMD TRC, SCTRL, load:

Specifically: DMD_TRC, DMD_SCTRL, DMD_LOADB

External [5-

Ω] series termination (at the transmitter)

DMD SAC and

Specifically: DMD_SAC_CLK, DMD_SAC_BUS, DMD_DAD_STRB,

miscellaneous control:

DMD_DAD_BUS

External [5-

Ω] series termination (at the transmitter)

DAD output enable:

Specifically: DMD_DAD_OEZ

External [0-

Ω] series termination

Instead this signal must be externally pulled-up to VDD_DMD through a 30- to

51-k

Ω resistor.

However, note that both the DLPC6401 output timing parameters and the DMD input timing parameters include

timing budget to account for their respective internal package routing skew. Thus, additional system margin can

be attained by comprehending the package variations and compensating for them in the PCB layout. To increase

system timing margin, TI recommends that DLPC6401 package variation be compensated for (by signal group),

but it may not be desirable to compensate for DMD package skew. Because, each DMD has a different skew

profile making the PCB layout DMD specific. Thus, if an OEM wants to use a common PCB design for different

DMDs, TI recommends that either the DMD package skew variation not be compensated for on the PCB or the

package lengths for all applicable DMDs be considered. Table 14 provides the DLPC6401 package output delay

at the package ball for each DMD I/F signal. DMD internal routing skew data is contained in the DMD data sheet.

Table 14. DLPC6401 DMD I/F Package Routing Length

SIGNAL

TOTAL DELAY (ps)

PACKAGE BALL

SIGNAL

TOTAL DELAY (ps)

PACKAGE BALL

DMD_D0

25.9

DMD_D14

B12

DMD_D1

19.6

DMD_D15

11.7

C12

DMD_D2

13.4

DMD_D16

4.7

D12

DMD_D3

7.4

DMD_D17

21.5

DMD_D4

18.1

B11

DMD_D18

24.8

A10

DMD_D5

11.1

C11

DMD_D19

8.3

DMD_D6

4.4

D11

DMD_D20

23.9

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