DLPC3433 datasheet(13/62 Pages) TI1

13 / 62 page

DLPC3433, DLPC3438

www.ti.com

DLPS035B – FEBRUARY 2014 – REVISED JANUARY 2016

Pin Functions – Clock and PLL Support

I/O

DESCRIPTION

NAME

NUMBER

Reference clock crystal input. If an external oscillator is used in place of a crystal, then this pin

PLL_REFCLK_I

I11

should be used as the oscillator input.

Reference clock crystal return. If an external oscillator is used in place of a crystal, then this pin

PLL_REFCLK_O

should be left unconnected (that is floating with no added capacitive load).

Pin Functions – Power and Ground(1)

DESCRIPTION

I/O

NAME

NUMBER

C5, D5, D7, D12, J4, J12, K3, L4, L12, M6,

VDD

PWR

Core power 1.1 V (main 1.1 V)

M9, D9, D13, F13, H13, L13, M10, D3, E3

VDDLP12

PWR

Core power 1.1 V

Common to all package types

C4, D6, D8, D10, E4, E13, F4, G4, G12, H4,

H12, J3, J13, K4, K12, L3, M4, M5, M8, M12,

G13, C6, C8

VSS

GND

Core ground (eDRAM, I/O ground, thermal ground)

Only available on DLPC343x

F6, F7, F8, F9, F10, G6, G7, G8, G9, G10,

H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6,

K7, K8, K9, K10

All 1.8-V I/O power:

(1.8-V power supply for all I/O other than the host or parallel

VCC18

C7, C9, D4, E12, F12, K13, M11

PWR

interface and the SPI flash interface. This includes RESETZ,

PARKZ LED_SEL, CMP, GPIO, IIC1, TSTPT, and JTAG pins)

Host or parallel interface I/O power: 1.8 to 3.3 V (Includes IIC0,

VCC_INTF

M3, M7, N3, N7

PWR

PDATA, video syncs, and HOST_IRQ pins)

Flash interface I/O power:1.8 to 3.3 V

VCC_FLSH

D11

PWR

(Dedicated SPI0 power pin)

VDD_PLLM

PWR

MCG PLL 1.1-V power

VSS_PLLM

RTN

MCG PLL return

VDD_PLLD

PWR

DCG PLL 1.1-V power

VSS_PLLD

RTN

DCG PLL return

(1)

The only power sequencing restrictions are:

(a) The VDDLP12 supply must be powered-on at exactly the same time or after the VDD11 supply.

(b) The VDD11 supply should ramp up with a 1-ms minimum rise time.

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