Data Sheet

ADF5355

REVISION HISTORY

2/15—Rev. 0 to Rev. A

Changed Register 5, Bit DB5 Value from 0 to 1 ........ Throughout

Changed Register 5 Default Value from 0x00800005 to

0x00800025 .................................................................... Throughout

Changed Register 8 Default Value from 0x102D4028 to

0x102D0428 ................................................................... Throughout

Changes to Table 1 ............................................................................4

Changed Timing Diagram Section to Write Timing Diagram

Section ................................................................................................7

Changes to Table 4 ..........................................................................10

Changes to Figure 4 to Figure 6 ....................................................11

Added Figure 7 to Figure 9; Renumbered Sequentially.............11

Changes to Figure 10 to Figure 18 ................................................12

Changes to Figure 20 ......................................................................13

Changes to Figure 23 and Figure 27 .............................................14

Changes to Figure 28 to Figure 30 and Figure 31 Caption........15

Changes to Reference Input Section and INT, FRAC, MOD,

and R Counter Relationship Section ............................................16

Changes to Phase Frequency Detector (PFD) and Charge Pump

Section ..............................................................................................17

Changes to VCO Section and Output Stage Section ..................18

Changes to Automatic Calibration (AUTOCAL) Section.........22

Changes to Figure 43 ......................................................................24

Changes to MUXOUT Section......................................................26

Changes to Reference Mode Section and Counter Reset

Section ..............................................................................................27

Changes to Negative Bleed Section...............................................28

Changes to Charge Pump Bleed Current Section.......................29

Changes to Register 9 Section, VCO Band Division Section,

Timeout Section, Automatic Level Calibration Timeout Section,

and Synthesizer Lock Timeout Section........................................31

Changes to ADC Conversion Clock (ADC_CLK_DIV)

Section ..............................................................................................32

Changes to Phase Resync Clock Divider Value Section and

Frequency Update Sequence Section............................................33

Changes to RF Synthesizer—A Worked Example Section ........34

Changes to Lock Time Section and Automatic Level

Calibration Timeout Section .........................................................35

Added Lock Time—A Worked Example Section .......................35

10/14—Revision 0: Initial Version

Rev. A | Page 3 of 38