AD9154-EBZ datasheet(43/124 Pages) AD

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Data Sheet

AD9154

Rev. B | Page 43 of 124

The method for setting the LMFCDel and LMFCVar is

described in the Link Delay Setup section.

Setting LMFCDel appropriately ensures that all the corresponding

data samples arrive in the same LMFC period. Then LMFCVar

is written into the receive buffer delay (RBD) to absorb all link

delay variation. This ensures that all data samples have arrived

before reading. By setting these to fixed values across runs and

devices, deterministic latency is achieved.

The RBD described in the JESD204B specification takes values

from 1 to K frame clock cycles, while the RBD of the AD9154

takes values from 0 PClock cycles to 10 PClock cycles. As a

result, up to 10 PClock cycles of total delay variation can be

absorbed. Because LMFCVar is in PClock cycles, and LMFCDel

is in frame clock cycles, a conversion between these two units is

needed. The PClockFactor, or number of frame clock cycles per

PClock cycle, is equal to 4/F. For more information on this

relationship, see the Clock Multiplication Relationships section.

Two examples follow that show how to determine LMFCVar

and LMFCDel. After they are calculated, write LMFCDel into

both Register 0x304 and Register 0x305 for all devices in the

system, and write LMFCVar to both Register 0x306 and

Link Delay Setup Example, With Known Delays

All the known system delays can be used to calculate LMFCVar

and LMFCDel as described in the Link Delay Setup section.

The example shown in Figure 54 is demonstrated in the

following steps according to the procedure outlined in the Link

Delay Setup section. Note that this example is in Subclass 1 to

achieve deterministic latency, which has a PClockFactor (4/F)

of 2 frame clock cycles per PClock cycle, and uses K = 32

(frames per multiframe). Because PCBFixed < PClockPeriod,

PCBFixed is negligible in this example and is not included in

the calculations.

1. Find the receiver delays using Table 8.

RxFixed = 17 PClock cycles

RxVar = 2 PClock cycles

2. Find the transmitter delays. The equivalent table in the

example JESD204B core (implemented on a GTH or GTX

transceiver on a Virtex-6 FPGA) states that the delay is

56 ± 2 byte clock cycles.

Because the PClockRate = ByteRate/4 as described in the

Clock Multiplication Relationships section, the transmitter

delays in PClock cycles are:

TxFixed = 54/4 = 13.5 PClock cycles

TxVar = 4/4 = 1 PClock cycle

3. Calculate MinDelayLane as follows:

MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)

= floor(17 + 13.5 + 0)

= floor(30.5)

MinDelayLane = 30

4. Calculate FALL_COUNT_DelayLane as follows:

FALL_COUNT_DelayLane = ceiling(RxFixed + RxVar +

TxFixed + TxVar + PCBFixed))

= ceiling(17 + 2 + 13.5 + 1 + 0)

= ceiling(33.5)

FALL_COUNT_DelayLane = 34

5. Calculate LMFCVar as follows:

LMFCVar = (FALL_COUNT_DelayLane + 1) − (MinDelay −

= (34 + 1) − (30 − 1) = 35 − 29

LMFCVar = 6 PClock cycles

6. Calculate LMFCDel as follows:

LMFCDel = ((MinDelay − 1) × PClockFactor) % K

= ((30 − 1) × 2) % 32 = (29 × 2) % 32

= 58 % 32

LMFCDel = 26 frame clock cycles

7. Write LMFCDel to both Register 0x304 and Register 0x305

for all devices in the system. Write LMFCVar to both

system.

Figure 54. LMFC_DELAY Calculation Example

FRAME CLOCK

LMFC

PCLOCK

DATA

DATA AT Tx FRAMER

ILAS

LMFCRX

TOTAL FIXED LATENCY = 30 PCLOCK CYCLES

LMFC DELAY = 26 FRAME CLOCK CYCLES

PCB FIXED

DELAY

DATA

ALIGNED LANE DATA

AT Rx DEFRAMER OUTPUT

ILAS

TOTAL VARIABLE

LATENCY = 4

PCLOCK CYCLES

Tx VAR

DELAY

Rx VAR

DELAY

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