AD9154 datasheet(66/124 Pages) AD

66 / 124 page

AD9154

Data Sheet

Rev. B | Page 66 of 124

Data Key NCO Alignment

In addition to supporting the SYSREF± alignment mode, the

AD9154 supports a mode where the NCO phase alignment

occurs when a user-specified pattern is seen at the DAC input.

The steps to achieve a data key NCO alignment are as follows:

1. Set NCOCLRMODE (Register 0x050, Bits[1:0]) = 0b10.

2. Write the expected 16-bit data key for the I and Q datapath

into NCOKEYIx (Register 0x051 to Register 0x052) and

NCOKEYQ (Register 0x053 to Register 0x054), respectively.

3. Set NCOCLRARM (Register 0x050, Bit 7) = 1.

4. Send the expected 16-bit I and Q data keys to the device to

achieve NCO alignment.

5. Check the alignment status. If the expected data key was seen

at the DAC input, then NCOCLRMTCH (Register 0x050,

Bit 5) = 1. If NCO phase alignment was successful,

NCOCLRPASS (Register 0x050, Bit 4) = 1. If phase

alignment failed, NCO_ALIGN_FAIL (Register 0x050,

Bit 3) = 1.

Multiple device NCO alignment can be achieved with the data

key alignment mode. To achieve multichip NCO alignment,

program the same expected data key on all devices, arm all

devices, and then send the data key to all devices/channels at

the same time.

NCO Alignment IRQ

An IRQ event showing whether the NCO align was tripped is

available.

Use Register 0x021, Bit 4 to enable DAC Dual A (DAC0 and

DAC1), and then use Register 0x025, Bit 4 to read back its status

and reset the IRQ signal.

Use Register 0x022, Bit 4 to enable DAC Dual B (DAC2 and

DAC3), and then use Register 0x026, Bit 4 to read back its status

and reset the IRQ signal.

See the Interrupt Request Operation section for more

information.

DOWNSTREAM PROTECTION

The AD9154 has several blocks designed to protect the power

amplifier (PA) in its board level signal chain, as well as other

downstream blocks. It consists of a power detection and

protection (PDP) block, a blanking state machine (BSM), and a

transmit enable state machine (Tx ENSM).

The PDP block monitors incoming data. If a moving average of

the data power goes above a threshold, the PDP block provides

a signal (PDP_PROTECT) that can be routed externally on the

PDP OUT0 and PDP OUT1 pins.

The Tx ENSM is a simpler block that controls delay between

TXENx and the Tx_PROTECT signal. The Tx_PROTECT

signal is used as an input to the BSM and its inverse can

optionally be routed externally. Optionally, the Tx ENSM can

also power down its associated DAC dual.

The BSM gently ramps data entering the DAC and flushes the

datapath. The BSM is activated by the Tx_PROTECT signal or

automatically by the LMFC sync logic during a rotation. Digital

gain must be enabled for proper function. Finally, some simple

logic takes the outputs from each of those blocks and uses them

to generate a desired PDP OUTx signal on an external pin. This

signal can be used to enable/disable downstream components,

such as a PA.

Power Detection and Protection

The input signal PDP block detects the average power of the

DAC input signal and to prevent overrange signals from being

passed to the next stage, which may potentially cause destructive

breakdown on power sensitive devices, such as PAs. The protection

function provides a signal (PDP_PROTECT) that can be routed

externally to shut down a PA.

The PDP block uses a separate path with a shorter latency than

the datapath to ensure that PDP_PROTECT gets triggered

before the overrange signal reaches the analog DAC cores. The

sum of the I2 and Q2 are calculated as a representation of the input

signal power (only the top seven MSBs of data samples are

used). The calculated sample power numbers are accumulated

through a moving average filter whose output is the average of

the input signal power in a certain number of samples. When the

output of the averaging filter is larger than the threshold, the

internal signal PDP_PROTECT goes high, which can optionally be

configured to trigger a signal on the PDP OUTx pins. The PDP

block is configured as shown in Table 71 and paged as described

in the Dual Paging section.

The choice of PDP_AVG_TIME (Register 0x062) and

PDP_THRESHOLD[12:0] (Register 0x060 to Register 0x061)

for effective protection are application dependent. Experiment

with real-world vectors to ensure proper configuration. The

PDP_POWER[12:0] readback (Register 0x063 to Register

0x064) can help by storing the maximum power when a set

threshold passes.

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