AL6562

Document Number: DS37542 Rev. 2 - 2

11 of 16

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February 2015

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AL6562

On the other hand, when the loading of PFC pre-regulator becomes low, the output voltage tends to stay steadily above the nominal value,

which is not the case when OVP is triggered by abrupt voltage increase. If this occurs, the E/A will saturate low, the external power transistor

is switched OFF, and the IC is put in idle state (static OVP). Normal operation is resumed as the error amplifier goes back into its linear region.

As a result, the device will work in burst-mode, with a repetition rate that can be very low. When either OVP is activated, the quiescent

consumption of the IC is reduced to minimum by the discharge of the capacitor and increases the hold-up capability of the IC supply.

THD (Total Harmonics Distortion)

The AL6562 reduces the THD by reducing conduction dead-angle occurring to the AC input current near the zero-crossings of the line voltage.

The important reason for this distortion to take place is the inability of the system to transfer energy effectively when the instantaneous line

voltage is very low, which is the case near line-voltage zero-crossing. This effect is magnified by the high-frequency filter capacitor placed after

the bridge rectifier, which retains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current

flow to temporarily stop.

To overcome this issue, the circuit section designed in the AL6562 forces the PFC regulator to process more energy near the line voltage

zero-crossings, as compared to that commanded by the control loop. This results in both minimizing the time interval when energy transfer is

lacking, and fully discharging the high-frequency filter capacitor after the bridge.

In essence, the circuit artificially increases the ON-Time of the Power Switch with a positive offset added to the output of the multiplier in the

proximity of the line voltage zero-crossings. This offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as

the line voltage moves towards the peak of the sinusoidal waveform.

Therefore, to maximize the benefit from the THD improvement circuit, the high-frequency filter capacitor after the bridge rectifier should be

minimized and kept to satisfy the EMI filtering requirements.

Non-Latched IC Disable (Enable)

Pin 1, INV, inverting input to the error amplifier, can be adapted to disable the system when the voltage on this pin is below 0.2V. In order to

restart the system, a voltage exceeding 0.45V must be applied. The ON/OFF control signal can be driven by a PWM controller and using an

NPN transistor to pin 1 to shut it down.