54AC377

Octal D Flip-Flop with Clock Enable

General Description

The ’AC/’ACT377 has eight edge-triggered, D-type flip-flops

with individual D inputs and Q outputs. The common buff-

ered Clock (CP) input loads all flip-flops simultaneously,

when the Clock Enable (CE) is LOW.

The register is fully edge-triggered. The state of each D in-

put, one setup time before the LOW-to-HIGH clock transi-

tion, is transferred to the corresponding flip-flop’s Q output.

The CE input must be stable only one setup time prior to the

LOW-to-HIGH clock transition for predictable operation.

Features

n Ideal for addressable register applications

n Clock enable for address and data synchronization

applications

n Eight edge-triggered D flip-flops

n Buffered common clock

n Outputs source/sink 24 mA

n See ’273 for master reset version

n See ’373 for transparent latch version

n ’ACT377 has TTL-compatible inputs

n Standard Microcircuit Drawing (SMD)

— ’AC377: 5962-88702

— ’ACT377: 5962-87697

Logic Symbols

Pin

Names

Description

D

Data Inputs

CE

Clock Enable (Active LOW)

Q

Data Outputs

CP

Clock Pulse Input

DS100290-1

IEEE/IEC

DS100290-2

February 1999

© 1999 National Semiconductor Corporation

DS100290

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