Connection Diagrams

Functional Description

The ’AC/’ACT374 consists of eight edge-triggered flip-flops

with individual D-type inputs and TRI-STATE true outputs.

The buffered clock and buffered Output Enable are common

to all flip-flops. The eight flip-flops will store the state of their

individual D inputs that meet the setup and hold time require-

ments on the LOW-to-HIGH Clock (CP) transition. With the

Output Enable (OE) LOW, the contents of the eight flip-flops

are available at the outputs. When the OE is HIGH, the out-

puts go to the high impedance state. Operation of the OE in-

put does not affect the state of the flip-flops.

Truth Table

Inputs

Outputs

D

n

CP

OE

O

n

H

N

LH

L

N

LL

XX

H

Z

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

Logic Diagram

Pin Assignment for DIP

and Flatpak

DS100289-3

Pin Assignment for LCC

DS100289-4

DS100289-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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