www.ams.com

Revision 1.0

9 - 20

AS8202B

Datasheet - Detailed Descr i p ti on

7 Detailed Description

The AS8202B is the first TTP controller to support both MFM and Manchester coding. Manchester coding is important for DC-free data

transmission, which allows the use of transformers in the data stream. The AS8202B is pin-compatible with its predecessor, the AS8202. The

AS8202B provides support for fault-tolerant, high-speed bus systems in a single device. The communication controller is qualified for the full

temperature range required for automotive applications and is certifiable according to RTCA standards. It offers superior reliability and supports

data transfer rates of 25 Mbit/s with MII and up to 4 Mbit/s with MFM/Manchester.

The CNI (communication network interface) forms a temporal firewall. It de-couples the controller network from the host subsystem by use of a

dual ported RAM (CNI). This prevents the propagation of control errors. The interface to the host CPU is implemented as a 16-bit wide non-

multiplexed asynchronous bus interface.

The TTP follows a conflict-free media access strategy called time division multiple access (TDMA). This means, TTP deploys a time slot

technique based on a global time that is permanently synchronized. Each node is assigned a time slot in which it is allowed to perform transmit

operation. The sequence of time slots is called TDMA round, a set of TDMA rounds forms a cluster cycle. The operation of the network is

repeated after one cluster cycle. The sequence of interactions forming the cluster cycle is defined in a static time schedule, called message

descriptor list (MEDL). The definition of the MEDL in conjunction with the global time determines the response time for a service request.

The membership of all nodes in the network is evaluated by the communications controller. This information is presented to all correct cluster

members in a consistent fashion. During operation, the status of all other nodes is propagated within one TDMA round. Please read more about

7.1 Host CPU Interface

The host CPU interface, also referred to as CNI (Communication Network Interface), connects the application circuitry to the AS8202B TTP

controller. All related signal pins provide an asynchronous read/write access to a dual ported RAM located in the AS8202B. There are no setup/

hold constraints referring to the microtick (main clock “CLK0”).

All accesses have to be executed on a granularity of 16-bit (2 byte), the device does not support byte-wide accesses. The pin A0 (LSB) of the

device differentiates even and odd 16-bit word addresses and is typically connected to A1 of a little-endian host CPU. The A0 of host CPU is not

connected to the device, and the application/driver on the host CPU should force all accesses to be 16-bit. For efficiency reasons, the host CPU

application/driver may access some memory locations of the AS8202B using wider accesses (e.g. 32-bit), and the bus interface of the host CPU

will automatically split the access into two consecutive 16-bit wide accesses to the TTP controller. Note that particularly in such a setup all timing

parameters of the host CPU interface must be met, especially the inactivity timeouts described as symbols 16–19.

The host interface features an interrupt or time signal INTB to notify the application circuitry of programmed and protocol-specific, synchronous

and asynchronous events.

The host CPU interface allows access to the internal instruction code memory. This is required for proper loading of the protocol execution code

into the internal instruction code RAM, for extensive testing of the instruction code RAM and for verifying the instruction code ROM contents.

INTB is an open-drain output, i.e. the output is only driven to '0' and is weak-pull-up at any other time, so external pull-up resistors or transistors

may be necessary depending on the application.

READYB is also an open-drain output, but with a possibility to be driven to ‘1’ for a defined time (selectable by register) before weak-pull-up at

any other time.

The LED port is software-configurable to automatically show some protocol-related states and events, see below for the LED port configuration.

Table 4. Host Interface Ports

Pin Name

Mode

Width

Comment

A[11:0]

in

12

CNI address bus, 12-bit (A0 is LSB)

D[15:0]

inout (tri)

16

CNI data bus, 16-bit (D0 is LSB)

CEB

in

1

CNI chip enable, active low

WEB

in

1

CNI write enable, active low

OEB

In

1

CNI output enable, active low

READYB

out (open drain)

1

CNI ready, active low

INTB

out (open drain)

1

CNI interrupt, time signal, active low

RAM_CLK_TESTSE

in

1

HOST clock

USE_RAM_CLK

in

1

HOST clock pin enable