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AS3695C датащи(PDF) 17 Page - ams AG |
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AS3695C датащи(HTML) 17 Page - ams AG |
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17 / 40 page ![]() AS3695C austriamicrosystems www.austriamicrosystems.com Rev 1.11 / 2010-12-08 16 - 39 4.2.8 Registers in PWM-generators RegAddr: 0x11 PWMREV1 Bit Name Description Default Acc ess 7:0 PWMrev 1 - 8 Selects PWM inverted operation for outputs 1 to 8 0...PWM normal 1... PWM inverted 00000000 r/w RegAddr: 0x12 PWMREV2 Bit Name Description Default Acc ess 7:0 PWMrev 9 - 16 Selects PWM inverted operation for outputs 9 to 16 0...PWM normal 1... PWM inverted 00000000 r/w RegAddr: 0x13 PWMCTRL Bit Name Description Default Acc ess 7 FaultDetDly Sets delay time between PWM=1 and fault detection start 0...120us 1...60us 0 r/w 6 DelayStart Defines when new PWM-Delay value takes effect 0...Delay values are updated every VSYNC pulse 1...Delay values are updated on the next VSYNC pulse only if HighTime or Delay value has been changed. 0 r/w 5 ClockSrc1 Clock source for internal PWM-generators 0..internal RC oscillator or HSYNC ( depending on ClockSrc0 ) 1...PLL output 0 r/w 4 VSYNCdet Enable VSYNC detection 0...VSYNC-detection OFF 1... VSYNC-detection ON. All current outpts are turned off if VSYNC signal is missing for 100ms 0 r/w 3 VSYNCedge Defines VSYNC trigger edge 0...VSYNC trigger on rising edge 1...VSYNC trigger on falling edge 0 r/w 2 PWMext Select external or internal PWM signal 0...PWM signal is generated internally 1...PWM signal is applied externally at pin VSYNC 0 r/w 1 UpdateMode Defines when internal registers are updated 0...Registers updated with rising edge of xCS 1...Registers updated with next VSYNC-edge 0 r/w 0 ClockSrc0 Clock source for internal PWM-generators 0..internal RC oscillator 1...External Pin HSYNC Note: This bit only takes effect when ClockSrc1 = 0 0 r/w RegAddr: PWMperiod 0x15 0x14 Bit Bit Description Default Access 3:0 7:0 PWMper[11:0] sets PWM period 0x00, 0x00 r/w RegAddr: PWM1delay 0x17 0x16 Bit Bit Description Default Access 3:0 7:0 PWM1del[11:0] sets PWM1 delay 0x00, 0x00 r/w RegAddr: PWM2delay 0x19 0x18 Bit Bit Description Default Access 3:0 7:0 PWM2del[11:0] sets PWM2 delay 0x00, 0x00 r/w RegAddr: PWM3delay 0x1B 0x1A |
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