AS3695A

austriamicrosystems

www.austriamicrosystems.com

Rev 1.10 / 2010-12-8

12 - 33

4.2.3 SPI data update, UPDATEmode bit

The PWM-settings that are programmed via the SPI-Interface take effect depending on the status of the

“UPDATEmode”-bit.

If UPDATEmode =1 new data from the serial interface are stored at the next rising edge of VSYNC

If UPDATEmode =0 new data from the serial interface are stored immediately after xCS goes high and

will take effect after current PWM cylce is finished. In this mode the values in the PWMxdel registers are

ignored. There will be no Delay on the PWM signals.

The PWMxHT-values are double buffered. HighTime values for the next VSYNC can be written even

when the current HighTime is not finished.

4.2.4 PWM direct control

The internal signals PWMx can also be direct applied at the VSYNC input if the bit PWMext=1.

4.2.5 VSYNC detect

The VSYNCdet=1 the VSYNC detector monitors the presence of a VSYNC signal. If If the VSYNC

signal is missing for more than 100ms the current outputs are temporary turned off.

4.2.6 VSYNC duration

Since the VSYNC input is connected to an edge detector, there is no restriction on the duration of the

VSYNC pulse.

4.2.7 Registers in PWM-generators

RegAddr: 0x11

PWMREV1

Bit

Name

Description

Default

Acc

ess

7:0

PWMrev

1 - 8

Selects PWM inverted operation for outputs 1 to 8

0...PWM normal

1... PWM inverted

00000000

r/w

RegAddr: 0x12

PWMREV2

Bit

Name

Description

Default

Acc

ess

7:0

PWMrev

9 - 16

Selects PWM inverted operation for outputs 9 to 16

0...PWM normal

1... PWM inverted

00000000

r/w

PWM-parameter update at third rising edge

VSYNC

clk

SCLK

SDI

xCS

PWM-parameter update. Takes effect after current PWM cycle has finished

If UPDATEmode = 0

If UPDATEmode = 1

No PW M update allowed