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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AS3510 датащи(PDF) 15 Page - ams AG |
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AS3510 датащи(HTML) 15 Page - ams AG |
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15 / 20 page  Product Brief AS3510 Rev. 1v2, June 2004 CONFIDENTIAL Page 14 of 19 Package and Pinning Pin Configuration for TQFP80 Pin# PinName Type Function 25 DVSS Supply Neg. supply of digital circuit 27 PVDD Supply Supply of peripheral levelshifter of digital inputs 28 DVDD Supply Pos. supply of digital circuits 29 MCLK Din with pull down Master clock 128*FS / left open - enables PLL 31 LRCK Din with pull down I2S_Left/Right FrameClock = FS 32 SCLK Din with pull down I2S_Serial data clock >=38*FS 33 SDI Din with pull down I2S_Serial data 18bit left oriented, first bit fix L 36 CSCL Din stt + spike supr I2Ccomp_Serial clock to access control register 37 CSDA Di/od stt + spike supr I2Ccomp_Serial data to access control register 38 SDO Dout_2mA I2S_Serial data 14bit left orieted, first bit fix L 39 USBon Dout_2mA USB_indication of usb supply present 40 RCV Dout_2mA USB_differential receiver output 41 VP Dout_2mA USB_signle ended pos. receiver output 42 VM Dout_2mA USB_signle ended neg. receiver output 43 VPO Din with pull down USB_transmitter pos. input 44 VMO Din with pull down USB_transmitter neg. input 45 OEN Din with pull up USB_transmitter output enable (low active) 46 DVSS Supply Neg. supply of digital circuit 47 DP Di/o with 1uA pd USB_pos. I/O terminal 48 DM Di/o with 1uA pd USB_neg. I/O terminal 49 VTRM Aout/Supply USB_3.2V termination voltage regulator output 50 UVDD Supply USB_external supply 4-5.5V 51 AUX_R Ain 40/200k to BGND Analog aux input to audio amp Right channel 52 AUX_L Ain 40/200k to BGND Analog aux input to audio amp Left channel 53 PWRUP Din 360k pull down Enable LDO1 and 2 and DCDC 54 PLDO3 Din_5state Selects one of 5 LDO3 states (L, 150kpd open, 150kpu, H) 55 MICP Ain 15k to agnd Microphone pos. input (MIC-ADC path) 56 MICN Ain 15k to agnd Microphone neg. input (MIC-ADC path) 57 VREF Ai/o 10uF decpl Reference voltage of DAC (AVDD) 58 AGND Ai/o 10uF decpl Reference voltage of DAC (AVDD/2) 59 AVSS Supply Neg. supply terminal of analog circuit 60 AVSS2 Supply 2nd Neg. supply terminal of analog circuit 64 AVDD Aout/Supply Pos. supply of analog circuits, LDO1 output – 2.9V 65 BGND Ai/o 100nF decp Reference voltage of power-amp (BVDD/2) 66 BVDD Supply Battery supply 3-5.5V 67 OUTR Aout Speaker/Headphone output (4 ohm min.) 68 BVSS Supply Neg. supply terminal of Power Amp. 69 OUTL Aout Speaker/Headphone output (4 ohm min.) 70 BVDD Supply Battery supply 3-5.5V 71 QLDO2 Aout LDO2 output – 2.9V to be connected to DVDD 72 QLDO3 Aout LDO3 output – 1.5…2.5V to be connected to PVDD 73 VSSDCDC Supply Power Ground for DCDC Converter 74 VSSDCDC Supply Power Ground for DCDC Converter 75 SWDCDC Aout Switch Output for DCDC Converter 76 SWDCDC Aout Switch Output for DCDC Converter 77 VB1V Supply Battery Supply Input (1V-3V) Table 18 Table of Pin Configuration for TQFP80 |
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