Connection Diagrams

Functional Description

The ’AC/’ACT174 consists of six edge-triggered D flip-flops

with individual D inputs and Q outputs. The Clock (CP) and

Master Reset (MR) are common to all flip-flops. Each D in-

put’s state is transferred to the corresponding flip-flop’s out-

put following the LOW-to-HIGH Clock (CP) transition. A LOW

input to the Master Reset (MR) will force all outputs LOW in-

dependent of Clock or Data inputs. The ’AC/’ACT174 is use-

ful for applications where the true output only is required and

the Clock and Master Reset are common to all storage

elements.

Truth Table

Inputs

Output

MR

CP

D

Q

LX

X

L

H

N

HH

H

N

LL

HL

X

Q

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Logic Diagram

Pin Assignment

for DIP and Flatpak

DS100277-3

Pin Assignment

for LCC

DS100277-4

DS100277-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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