54AC109

Dual JK Positive Edge-Triggered Flip-Flop

General Description

The ’AC/’ACT109 consists of two high-speed completely in-

dependent transition clocked JK flip-flops. The clocking op-

eration is independent of rise and fall times of the clock

waveform. The JK design allows operation as a D flip-flop

(refer to ’AC/’ACT74 data sheet) by connecting the J and K

inputs together.

Asynchronous Inputs:

LOW input to S

LOW input to C

Clear and Set are independent of clock

Simultaneous LOW on C

HIGH

Features

n Outputs source/sink 24 mA

n ’ACT109 has TTL-compatible inputs

n Standard Military Drawing (SMD)

— ’AC109: 5962-89551

— ’ACT109: 5962-88534

Logic Symbol

Pin Names

Description

J

Data Inputs

CP

Clock Pulse Inputs

C

Direct Clear Inputs

S

Direct Set Inputs

Q

Outputs

DS100267-1

DS100267-2

IEEE/IEC

DS100267-7

August 1998

© 1998 National Semiconductor Corporation

DS100267

www.national.com