Z89321 datasheet(13/40 Pages) ZILOG

13 / 40 page

Z89321/371/391

Zilog

16-Bit Digital Signal Processors

DS97DSP0100

P R E L I M I N A R Y

AC ELECTRICAL CHARACTERISTICS

(VDD= 5V ±10%, TA = Ð40°C to +85°C, unless otherwise specified.)

fclock = 20 MHz1

Symbol

Parameter

Min

Max

Clock

TCY

Clock Cycle Time

Clock Rise Time

Clock Fall Time

CPW

Clock Pulse Width

I/O

DSVALID

/DS Valid Time from CLOCK Fall

DSHOLD

/DS Hold Time from CLOCK Rise

EASET

EA Setup Time to /DS Fall

EAHOLD

EA Hold Time from /DS Rise

RDSET

Data Read Setup Time to /DS Rise

RDHOLD

Data Read Hold Time from /DS Rise

WRVALID

Data Write Valid Time from /DS Fall

WRHOLD

Data Write Hold Time from /DS Rise

Interrupt

INTSET

Interrupt Setup Time to CLOCK Fall

INTWIDTH

Interrupt Low Pulse Width

1 TCY

CODEC Interface

SSET

SCLK Setup Time from Clock Rise

FSSET

FSYNC Setup Time from SCLK Rise

TXSET

TXD Setup Time from SCLK Rise

RXSET

RXD Setup Time to SCLK Fall

RXHOLD

RXD Hold Time from SCLK Fall

Reset

RRISE

Reset Rise Time

1000

RSET

Reset Setup Time to CLOCK Rise

RWIDTH

Reset Low Pulse Width

2 TCY

External Program Memory

PAVALID

PA Valid Time from CLOCK Rise

PDSET

PD Setup Time to CLOCK Rise

PDHOLD

PD Hold Time from CLOCK Rise

Wait State

WSET

WAIT Setup Time to CLOCK Rise

WHOLD

WAIT Hold Time from CLOCK Rise

Halt

HSET

Halt Setup Time to CLOCK Rise

HHOLD

Halt Hold Time from CLOCK Rise

Note:

1. Z89321 only

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