Z86C9620VSC datasheet(13/46 Pages) ZILOG

13 / 46 page

Z86C61/62/96

Z8® MICROCONTROLLER

and P35 are used as the handshake control /DAV0 and

RDY0 (Data Available and Ready). Handshake signal

assignment is dictated by the I/O direction of the upper

nibble P07-P04. The lower nibble must have the same

direction as the upper nibble to be under handshake

control.

For external memory references, Port 0 can provide ad-

dress bits A11-A8 (lower nibble) or A15-A8 (lower and

upper nibble) depending on the required address space.

If the address range requires 12 bits or less, the upper

nibble of Port 0 can be programmed independently as I/O

while the lower nibble is used for addressing. If one or both

nibbles are needed for I/O operation, they must be config-

ured by writing to the Port 0 Mode register.

In ROMless mode, after a hardware reset, Port 0 lines are

defined as address lines A15-A8, and extended timing is

set to accommodate slow memory access. The initializa-

tion routine includes reconfiguration to eliminate this ex-

tended timing mode (Figure 10).

/P0DS

Port 0 Data Strobe (output, active Low). Signal used

to emulate Port 0 when in ROMless mode.

/P1DS

Port 1 Data Strobe (output, active Low). Signal used

to emulate Port 1 when in ROMless mode.

/DTIMERS

Disable Timers (input, active Low). All timers

are stopped by the Low level at this pin. This pin has an

internal pull up resistor.

SCLK (output). System clock pin.

/SYNC

Instruction SYNC Signal (output, active Low). This

signal indicates the last clock of the current executing

instruction.

Port 0 (P07-P00). Port 0 is an 8-bit, nibble programmable,

bidirectional, TTL compatible port. These eight I/O lines

can be configured under software control as a nibble I/O

port, or as an address port for interfacing external memory.

When used as an I/O port, Port 0 may be placed under

handshake control. In this configuration, Port 3, lines P32

OEN

Out

PAD

Port 0 (I/O)

Handshake Controls

/DAV0 and RDY0

(P32 and P35)

MCU

TTL Level Shifter

Auto Latch

≈ 500 KΩ

Figure 10. Port 0 Configuration

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