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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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Z86C40 датащи(PDF) 13 Page - Zilog, Inc. |
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Z86C40 датащи(HTML) 13 Page - Zilog, Inc. |
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13 / 17 page  CP96DZ82900 13 Z86C30/C31/C32/C40 CP96DZ82900 ZILOG AC CHARACTERISTICS External I/O or Memory Read and Write Timing Table (Z86C40 Only) (SCLK/TCLK = XTAL/2) T A=–40°C to 105°CTA = –40°C to +105°C Note [3] 12 MHz 16 MHz 12 MHz 16 MHz No Symbol Parameter V CC Min Max Min Max Min Max Min Max Units Notes 1 TdA(AS) Address Valid to /AS Rise Delay 3.0 35 25 35 25 ns [2] 5.5 35 25 35 25 ns 2 TdAS(A) /AS Rise to Address Float Delay 3.0 45 35 45 35 ns [2] 5.5 45 35 45 35 ns 3 TdAS(DR) /AS Rise to Read Data Req’d Valid 3.0 250 180 250 180 ns [1,2] 5.5 250 180 250 180 ns 4 TwAS /AS Low Width 3.0 55 40 55 40 ns [2] 5.5 55 40 55 40 ns 5 TdAS(DS) Address Float to /DS Fall 3.0 0 0 0 0 ns 5.5 00 00ns 6 TwDSR /DS (Read) Low Width 3.0 200 135 200 135 ns [1,2] 5.5 200 135 200 135 ns 7 TwDSW /DS (Write) Low Width 3.0 110 80 110 80 ns [1,2] 5.5 110 80 110 80 ns 8 TdDSR(DR) /DS Fall to Read Data Req’d Valid 3.0 150 75 150 75 ns [1,2] 5.5 150 75 150 75 ns 9 ThDR(DS) Read Data to /DS Rise Hold Time 3.00 0 0 0 0 ns [2] 5.5 00 00ns 10 TdDS(A) /DS Rise to Address Active Delay 3.0 45 50 45 50 ns [2] 5.5 55 50 55 50 ns 11 TdDS(AS) /DS Rise to /AS Fall Delay 3.0 30 35 30 35 ns [2] 5.5 45 35 45 55 ns 12 TdR/W(AS) R//W Valid to /AS Rise Delay 3.0 45 25 45 25 ns [2] 5.5 45 25 45 25 ns 13 TdDS(R/W) /DS Rise to R//W Not Valid 3.0 45 35 45 35 ns [2] 5.5 45 35 45 35 ns 14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 3.0 55 25 55 25 ns [2] 5.5 55 25 55 25 ns 15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 3.0 45 35 45 35 ns [2] 5.5 45 35 45 35 ns 16 TdA(DR) Address Valid to Read Data Req’d Valid 3.0 310 230 310 230 ns [1,2] 5.5 310 230 310 230 ns 17 TdAS(DS) /AS Rise to /DS Fall Delay 3.0 65 45 65 45 ns [2] 5.5 65 45 65 45 ns 18 TdDM(AS) /DM Valid to /AS Fall Delay 3.0 35 30 35 30 ns [2] 5.5 35 30 35 30 ns 19 TdDS(DM) /DS Rise to DM Valid Delay 3.0 45 35 45 35 ns 5.5 45 35 45 35 ns 20 ThDS(AS) /DS Valid to Address Valid Hold Time 3.0 45 35 45 35 ns 5.5 45 35 45 35 ns Notes: [1] When using extended memory timing add 2 TpC. [2] Timing numbers given are for minimum TpC. [3] The V CC voltage specification of 3.0V guarantees 3.3V ± 0.3V, and the V DD voltage specification of 5.5V guarantees 5.0V ± 0.5V. Standard Test Load All timing references use 0.7 V CC for a logic 1 and 0.2 VCC for a logic 0. For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0. |
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