OPA659

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SBOS342C – DECEMBER 2008 – REVISED NOVEMBER 2015

11 Layout

11.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier such as the OPA659 requires careful attention to

PCB layout parasitics and external component types. Recommendations that can optimize device performance

include the following

1. Minimize parasitic capacitance to any AC ground for all of the signal input/output (I/O) pins. Parasitic

capacitance on the output and inverting input pins can cause instability: on the noninverting input, it can react

with the source impedance to cause unintentional band-limiting. To reduce unwanted capacitance, a window

around the signal I/O pins should be opened in all of the ground and power planes around those pins.

Otherwise, ground and power planes should be unbroken elsewhere on the board.

2. Minimize the distance (less than 0.25 inches, or 6.35 mm) from the power-supply pins to the high-

frequency, 0.1-

μF decoupling capacitors. At the device pins, the ground and power plane layout should not

be in close proximity to the signal I/O pins. Use a single point ground, located away from the input pins, for

the positive and negative supply high-frequency, 0.1-

μF decoupling capacitors. Avoid narrow power and

ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply

connections should always be decoupled with these capacitors. Larger (2.2

μF to 10 μF) decoupling

capacitors, effective at lower frequencies, should also be used on the supply pins. These larger capacitors

may be placed somewhat farther from the device and may be shared among several devices in the same

area of the PCB.

3. Careful selection and placement of external components preserves the high-frequency performance

of the OPA659. Resistors should be a very low reactance type. Surface-mount resistors work best and allow

a tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good

high-frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use

wirewound-type resistors in a high-frequency application. The inverting input pin is the most sensitive to

parasitic capacitance; consequently, always position the feedback resistor as close to the negative input as

possible. The output is also sensitive to parasitic capacitance; therefore, position a series output resistor (in

termination resistors, should also be placed close to the package. Even with a low parasitic capacitance,

excessively high resistor values can create significant time constants that can degrade device performance.

Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For

resistor values greater than 1.5 k

Ω, this parasitic capacitance can add a pole and/or zero below 500 MHz

that can affect circuit operation. Keep resistor values as low as possible, consistent with load driving

noise terms remain low, and minimizes the effects of the parasitic capacitance. Transimpedance applications

(for example, see Figure 39) can use the feedback resistor required by the application as long as the

feedback compensation capacitor is set given consideration to all parasitic capacitance terms on the

inverting node.

4. Connections to other wideband devices on the board may be made with short direct traces or through

onboard transmission lines. For short connections, consider the trace and the input to the next device as a

lumped capacitive load. Relatively wide traces (50 mils to 100 mils, or 1.27 cm to 2.54 cm) should be used.

unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated

transmission line is acceptable, implement a matched impedance transmission line using microstrip or

stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-

Ω

environment is normally not necessary onboard, and in fact a higher impedance environment improves

distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined

based on board material and trace dimensions, a matching series resistor into the trace from the output of

the OPA659 is used as well as a terminating shunt resistor at the input of the destination device. Remember

also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance

of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-

dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-

terminated at the source end only. Treat the trace as a capacitive load in this case, and set the series

resistor value as shown in Figure 24. This configuration does not preserve signal integrity as well as a

doubly-terminated line. If the input impedance of the destination device is low, there will be some signal

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