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SPG-FE-LX-IDFC датащи(PDF) 7 Page - Source Photonics, Inc.

номер детали SPG-FE-LX-IDFC
подробное описание детали  Built-in PHY supporting SGMII Interface
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производитель  SOURCE [Source Photonics, Inc.]
домашняя страница  http://www.sourcephotonics.com
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SPG-FE-LX-IDFC датащи(HTML) 7 Page - Source Photonics, Inc.

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DS-7362 Rev 02 2013-11-21
SPG-FE-LX-IDFC
SPG-FE-LX-CDFC
Recommended Software configuration
How to configure auto-negotiation, loopback, work speed
The module can support auto-negotiation, loopback configuration.
Please refer the following steps to configure:
Step 1: Access the module at 0xA2 via two-wire serial interface.
Step 2: Configure 0x6Dh/6Eh (Byte 109~110) as below table. Addr.109 default is “5Fh”. Addr.110 default is
“00h”.
Addr. 109
Function
“1”
“0”
Default Value
(BIN)
bit7
FEFI Status
FEFI condition detected
FEFI
condition
not
detected
‘0’
bit6
Fiber
Auto-Negotiation
Disable
Enable
‘1’
Bit5
MAC
Auto-Negotiation
Disable
Enable
‘0’
bit4
FEFI function
Disable
Enable
‘1’
bit3
CRC checker
Disable/Reset
Enable
‘1’
bit2
Fiber loop back
Disable
Enable
‘1’
bit1
MAC loop back
Disable
Enable
‘1’
bit0
Reserved
Reserved
Reserved
‘1’
Addr. 110
Function
“1”
“0”
Default Value
(BIN)
bit7
TX Disable State
TX-Disable
TX-Enable
‘0’
bit6
TX-Disable
TX-Disable
TX-Enable
‘0’
Bit5~Bit4
Reserved
Reserved
Reserved
‘0’
Bit3
Work speed mode
1000Base
100Base
‘0’
Bit2
TX fault output
status
TX fault indication
No fault
‘0’
Bit1
LOS pin output
status
LOS asserted
(Link down)
LOS de-asserted
(Link up)
‘0’
Bit0
Data Ready status
Not ready
Ready
‘0’
Notes: “1” is invalid for Bit 3 in address 110(work speed is only 100Base).
Monitoring Specification
The digital diagnostic monitoring interface also defines another 256-byte memory map in EEPROM,
which makes use of the 8 bit address 1010001X (A2h). Please see
Figure 4
. For detail EEPROM information, please refer to the related document of
SFF-8472 Rev 9.5. The monitoring specification of this product is described in Table 8.



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