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TECHNICAL DATA SHEET

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inventory and certifications: 60 GHz Receiver (Rx) Waveguide Module PEM002

PEM002

60 GHz Receiver (Rx) Waveguide Module

PEM002 REV

Digital Control Registers and Serial Interface Protocol - Read Operation

Figure 6 shows the sequence of control signals at the ENABLE, CLOCK and DATA pins to read a single byte at a register

location. A read operation requires a 27 bit field: The first 18 bits are used to clock in the bits on the DATA input pin. The first 8

bits during a read operation are “don’t care” bits as they are placeholders for the 8-bit byte data which would be present during

a write operation. The following 10 bits are composed of the byte address (BYTE 0 through BYTE 15, 000000 to 001111, LSB

first, only 4 of the 6 bits are used with the two MSBs set to 0), the read/write (R/W) bit (read = 0), and the module address which

distinguishes between a transmitter module and receiver module (for the PEM002 receiver, RX module = 111).

After clock pulse 17 (18 total pulses), the ENABLE signal is returned to a high state while the clock signal is low, then a single

clock pulse (pulse 18) is sent during the ENABLE signal high period. The ENABLE signal then returns to the low state while

the CLOCK signal is low. At each of the subsequent 8 CLOCK pulses, the 8-bit data from the specified register location is

available at the SCANOUT pin, LSB first. Note that the DATA signal must remain in the low state during the period from clock

pulse 18 through 26. Following clock pulse 26, the ENABLE signal goes high while the CLOCK signal is low to end the read

operation.

ENABLE

CLOCK

0

1

2

17

DATA

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17

SCAN OUT

0

1

2

3

4

5

6

7

26

Read Data

18

Data

Byte Address

R/W TX/RX Module

Figure 6 Read Operation Timing Diagram