MPC8264ACVR datasheet(20/48 Pages) MOTOROLA

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MPC826xA (HiP4) Family Hardware Speciﬁcations

MOTOROLA

Clock Conﬁguration Modes

NOTE

The UPM machine outputs change on the internal tick determined by the

memory controller programming; the AC speciﬁcations are relative to the

internal tick. Note that SDRAM and GPCM machine outputs change on

CLKin’s rising edge.

1.3

Clock Conﬁguration Modes

To conﬁgure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the

MODCK[1–3] pins are sampled while HRESET is asserted. Table 12 lists the eight basic conﬁguration

modes. Table 13 lists the other modes that are available by using the conﬁguration pin (RSTCONF) and

driving four bits from hardware conﬁguration word on the data bus.

Note that the MPC8265 and the MPC8266 have two additional clocking modes—PCI agent and PCI host.

Refer to Section 1.3.2, “PCI Mode” on page 23 for information.

NOTE

Clock conﬁgurations change only after POR is asserted.

1.3.1

Local Bus Mode

Table 12 describes default clock modes for the MPC826xA.

Table 13 describes all possible clock conﬁgurations when using the hard reset conﬁguration sequence.

Note that basic modes are shown in boldface type. The frequencies listed are for the purpose of illustration

only. Users must select a mode and input bus frequency so that the resulting conﬁguration does not exceed

the frequency rating of the user’s device.

Table 12. Clock Default Modes

MODCK[1–3]

Input Clock

Frequency

CPM Multiplication

Factor

CPM

Frequency

Core Multiplication

Factor

Core

Frequency

000

33 MHz

100 MHz

133 MHz

001

33 MHz

100 MHz

166 MHz

010

33 MHz

133 MHz

011

33 MHz

133 MHz

166 MHz

100

66 MHz

133 MHz

2.5

166 MHz

101

66 MHz

133 MHz

200 MHz

110

66 MHz

2.5

166 MHz

2.5

166 MHz

111

66 MHz

2.5

166 MHz

200 MHz

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