MPC8264AVR datasheet(5/48 Pages) MOTOROLA

5 / 48 page

MOTOROLA

MPC826xA (HiP4) Family Hardware Speciﬁcations

Features

– Supports two groups of four TDM channels for a total of eight TDMs

– 2,048 bytes of SI RAM

– Bit or byte resolution

– Independent transmit and receive routing, frame synchronization

– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN

primary rate, Motorola interchip digital link (IDL), general circuit interface (GCI), and

user-deﬁned TDM serial interfaces

— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,

SCCs, SMCs, and serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

Additional features of the MPC826xA family are as follows:

•

CPM

— 32-Kbyte dual-port RAM

— Additional MCC host commands

— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support

inverse multiplexing for ATM capabilities (IMA) (MPC8264 and MPC8266 only)

•

CPM multiplexing

— FCC2 can also be connected to the TC layer.

•

TC layer (MPC8264 and MPC8266 only)

— Each of the 8 TDM channels is routed in hardware to a TC layer block

– Protocol-speciﬁc overhead bits may be discarded or routed to other controllers by the SI

– Performing ATM TC layer functions (according to ITU-T I.432)

– Transmit (Tx) updates

– Cell HEC generation

– Payload scrambling using self synchronizing scrambler (programmable by the user)

– Coset generation (programmable by the user)

– Cell rate by inserting idle/unassigned cells

– Receive (Rx) updates

– Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA

parameters for the delineation state machine

– Payload descrambling using self synchronizing scrambler (programmable by the user)

– Coset removing (programmable by the user)

– Filtering idle/unassigned cells (programmable by the user)

– Performing HEC error detection and single bit error correction (programmable by user)

– Generating loss of cell delineation status/interrupt (LOC/LCD)

— Operates with FCC2 (UTOPIA 8)

— Provides serial loop back mode

— Cell echo mode is provided

— Supports both FCC transmit modes

– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.

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