Frame 1 two-wire slave address byte

Frame 2 pointer register byte

Frame 4 data byte 2

1

Start by

master

ACK by

device

ACK by

device

ACK by

device

Stop by

master

1

9

1

1

D7

D6

D5

D4

D3

D2

D1

D0

9

Frame 3 data byte 1

ACK by

device

1

D7

SDA

(Continued)

SCL

(Continued)

D6

D5

D4

D3

D2

D1

D0

9

9

SDA

SCL

0

0

1

0

A1

(1)

A0

(1)

R/W

0

0

0

0

0

0

P1

P0

¼

¼

SCL

SDA

t

(LOW)

t

RC

t

FC

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

t

(BUF)

S

S

P

P

t

RD

t

FD

TMP112-Q1

www.ti.com

SLOS887D – SEPTEMBER 2014 – REVISED DECEMBER 2015

7.3.2.9 Timing Diagrams

various operations on the TMP112-Q1 device. Parameters for Figure 10 are listed in the Timing Requirements

table. The bus definitions are defined as follows:

Bus Idle:

Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low, when the SCL line is high, defines

a START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a

STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. Using the TMP112-Q1 device for single byte updates is also

possible. To update only the most-significant (MS) byte, terminate the communication by issuing a

START or STOP communication on the bus.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device

that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of the acknowledge clock pulse. Setup and

hold times must be taken into account. On a master receive, the termination of the data transfer

can be signaled by the master generating a not-acknowledge (1) on the last byte that has been

transmitted by the slave.

7.3.2.9.1

Two-Wire Timing Diagrams

See the Timing Requirements table for timing specifications.

Figure 10. Two-Wire Timing Diagram

(1)

The values of A0 and A1 are determined by the ADD0 pin.

Figure 11. Two-Wire Timing Diagram for Write Word Format

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