PDSP16116

6

NORMAL MODE OPERATION

When the MBFP mode select input is held low the ‘Normal’

mode of operation is selected. This mode supports all complex

multiply operations that do not require block floating point

arithmetic.

Complex two’s complement fractional data is loaded into the

X and Y input registers via the X and Y Ports on the rising edge

of CLK. The X and Y port registers are individually enabled by

quired to be permanently enabled, then these signals may be

tied to ground.

The Real and Imaginary components of the fractional data

are each assumed to have the following format:

Bit Number

15

Weighting

14 13 12 11 10

9

76543210

S

2

2

2

2

2

2

2

2

2

2

2

2

2

2

8

2

Multiplier Stage

On each clock cycle the contents of the input registers are passed

to the four multipliers to start a new complex multiply operation.

Each complex multiply operation requires four partial products

(XR3YR), (XR3YI), (XI3YR), (XI3YI), all of which are calculated

in parallel by the four 16316 multipliers. Only one clock cycle is

required to complete the multiply stage before the multiplier results

are loaded into the multiplier output registers for passing on to the

adder/ subtractors in the next cycle. Each multiplier produces a 31-

bit result with the duplicate sign bit eliminated. The format of the

output data from the multipliers is:

Bit Number

30

Weighting

29 28 27 26 25 24

76543210

S

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Adder/Subtractor Stage

The 31-bit real and imaginary results from the multipliers

are passed to two 32-bit adder/subtractors. The adder calcu-

lates the imaginary result [(XR 3 YI) 1 (XI 3 YR)] and the

Rounding

The ROUND control when asserted rounds the most

significant 16 bits of the full 32-bit result from the shifter. If the

ROUND signal is active (high), then bit 16 is set to ‘1’, rounding

the most significant 16 bits of the shifted result. (The least

significant 16 bits are unaffected). Inserting a ‘1’ ensures that

the rounding error is never greater than 1 LSB and that no DC

bias is introduced as a result of the rounding processes. The

format of the rounded result is:

Bit Number

30

Weighting

29 28 27

17 16 15 14 13

2

1

0

S

2

2

2

2

2

2

2

2

2

2

2

2

0

31

18

2

ROUNDED VALUE

LSBs

Bit Number

30

Weighting

29 28 27 26

76543210

S

2

2

2

2

2

2

2

2

2

2

2

2

2

0

31

8

2

subtractor calculates the real result (XR 3 YR) = (XI 3 YI).

Each adder/subtractor produces a 32-bit result with the

following format:

Result Correction

Due to the nature of the fraction two’s complement repre-

sentation it is possible to represent 21 exactly but not 11. With

conventional multipliers this causes a problem when 21 is mul-

tiplied by 21 as the multiplier produces an incorrect result. The

PDSP16116 includes a trap to ensure that the most positive

the incorrect result. The multiplier result is therefore always a

correct fractional value. Fig.2 shows the value ‘1’ being multi-

plexed into the data path controlled by four comparators.

Complex Conjugation

Either the X or Y input data may be complex conjugated by

asserting the CONX or CONY signals respectively. Asserting

either of these signals has the effect of inverting (multiplying

by 21 ) the imaginary component of the respective input. Table 3

shows the effect of CONX and CONY on the X and Y inputs.

Table 3 Conjugate functions

CONY

CONX

Low

High

Low

High

Low

Low

High

High

Function

(XR 1 XI)3(YR 1 YI)

(XR 2 XI)3(YR 1 YI)

(XR 1 XI)3(YR 2 YI)

Invalid

Operation

X 3 Y

Conj. X 3 Y

X 3 Conj. Y

Invalid