Advance Information

MT9300

21

Bit

Name

Description

7

IRQ

Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt

FIFO register is read.

Logic Low indicates that no interrupt is pending and the FIFO is empty.

6:5

0

Unused bits. Always zero

4:0

I<4:0>

I<4:0> binary code indicates the channel number at which a Tone Detector state

change has occurred.

Note: Whenever a Tone Disable is detected or released, an interrupt is generated.

Bit

Name

Description

7:1

res

Reserved bits. Must always be set to zero for normal operation.

0

Tirq

Test IRQ: Useful for the application engineer to verify the interrupt service routine.

When high, any change to MTDBI and MTDAI bits of the Main Control Register will

cause an interrupt and its corresponding channel number will be available from the

Interrupt FIFO Register.

When low, normal operation is selected.

Interrupt FIFO Register

I0

I1

I2

I3

I4

0

0

IRQ

76543210

Reset Value:

Read Address:

Test Register

Tirq

res

res

res

res

res

res

res

76543210

Reset Value: