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MT9174AE датащи(PDF) 3 Page - Mitel Networks Corporation

номер детали MT9174AE
подробное описание детали  ISO2-CMOS ST-BUS??FAMILY Digital Network Interface Circuit with Receive Sync Marker Bit
PDF  4 Pages
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производитель  MITEL [Mitel Networks Corporation]
домашняя страница  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MT9174AE датащи(HTML) 3 Page - Mitel Networks Corporation

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Advance Information
MT9174
9-157
15
17
F0o/RCK
Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device to
allow daisy chaining. In MOD mode provides the receive bit rate clock to the system.
16
19
C4/TCK
Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible clock
input for the MASTER and output for the SLAVE in DN mode. For MOD mode this pin
provides the transmit bit rate clock to the system.
17
21
OSC2
Oscillator Output. CMOS Output.
19
22
OSC1
Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical
Characteristics for OSC1 input requirements.
20
23
Precan
Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the
precanceller is forced to VBias thus bypassing the precanceller section. When logic ’0’,
the LOUT to the precanceller path is enabled and functions normally. An internal
pulldown (50 k
Ω) is provided on this pin.
18
1,6,
18,
20,
25
NC
No Connection. Leave open circuit
21
24
LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When
logic “0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on this pin.
22
26
TEST
Test Pin.
Connect to VSS.
23
27
LIN
Receive Signal input (Analog).
24
28
VDD
Positive Power Supply (+5V) input.
Pin Description (continued)
Pin #
Name
Description
24
28



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