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SM5859AF датащи(PDF) 23 Page - Nippon Precision Circuits Inc

номер детали SM5859AF
подробное описание детали  compression and non compression type antishock memory controller
PDF  33 Pages
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производитель  NPC [Nippon Precision Circuits Inc]
домашняя страница  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5859AF датащи(HTML) 23 Page - Nippon Precision Circuits Inc

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SM5859AF
NIPPON PRECISION CIRCUITS-23
Correct data demodulation becomes impossible for
the CD signal processor IC when a disturbance
exceeding the RAM jitter margin occurs. The
YFLAG signal input pin is used to indicate when
such a condition has occurred.
The YFCLK signal is a 7.35 kHz clock synchronized
to the CD format frame 1.
The IC checks the YFLAG input and stops the
encode sequence when such a disturbance has
occurred, and then makes FLAG6 active.
The YFLAG check method used changes depend-
ing on the YFLGS flag and YFCKP flag (85H com-
mand). See table1.
If YFLGS is set to 1, then YFCLK should be tied
either High or Low.
YFLAG, YFCLK, FLAG6
85H command
YFLGS
YFCKP
FLAG6 set conditions
FLAG6 reset conditions
1
0
0
When YFLAG=LOW on YFCLK input falling edge
- By status read (90H command)
2
1
When YFLAG=LOW on YFCLK input rising edge
- When MSON=LOW
3
1
0
When YFLAG=LOW
YFCLK be tied either High or Low
- After system reset
4
1
When YFLAG=HIGH
Table1. YFLAG signal check method



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