MT8924

Preliminary Information

8-6

Table 1 - PCM Noise Suppression Threshold Levels

Noise

Threshold

PCM Byte

+ve input

-ve input

B7 - B0

B7 - B0

A-Law

1/4096

1000 0000

0000 0000

9/4096

1000 0100

0000 0100

16/4096

1000 1000

0000 1000

32/4096

1000 1111

0000 1111

µ-Law

1/8159

1111 1111

0111 1111

9/8159

1111 1011

0111 1011

16/8159

1111 0111

0111 0111

32/8159

1111 0000

0111 0000

Table 2 - PCM Byte Format

B7 (sign bit) is the MSB and B0 is the LSB

F1-F0 corresponds to the D5-D4 bits of the control byte of Operating Mode Instruction 5

F1

F0

B7

B6

B5

B4

B3

B2

B1

B0

Comments

00

+ Full Scale

11111111

No Inversion

+ 0 Level

10000000

- 0 Level

00000000

- Full Scale

01111111

01

+ Full Scale

10101010

Even Bit Inversion

+ 0 Level

11010101

- 0 Level

01010101

- Full Scale

00101010

10

+ Full Scale

11010101

Odd Bit Inversion

+ 0 Level

10101010

- 0 Level

00101010

- Full Scale

01010101

11

+ Full Scale

10000000

Bit Inversion

+ 0 Level

11111111

- 0 Level

01111111

- Full Scale

00000000

Overflow Detection / Input Channel Attenuation

If

the

sum

of

the

channels

involved

in

one

conference exceeds the full scale value of the

accumulator, an overflow condition is generated

which can be monitored specifically by reading the

status of the overflow register. If an overflow

condition occurs, then each channel in a conference

can be independently attenuated if desired.

Alternatively, a conference in the overflow condition

can be detected using the OS signal in conjunction

with frame pulse F0i. OS will be low during the

second half of a general output channel slot time N,

if channel N belongs to a conference in overflow (see

Figure 11). This information can be used to control

input channel attenuation through software control.